History

(1)Architecture of the IBM System/360

(2) Parallel Operation in the Control Data 6600

(3) Cramming More Components onto Integrated Circuits

also read pages 1-16 of the text (pages 1-55 in total)

History 2

(1) The CRAY-1 Computer System

(2) CRAY-1 Computer Technology

(3) The History of the Microcomputer -- Invention and Evolution

April 9

Branch Prediction

(1) Two-Level Adaptive Training Branch Prediction

(2) The YAGS branch prediction scheme

Branch Prediction

(1) Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor

(2) Neural Methods for Dynamic Branch Prediction

Branch Prediction

(1) The L-TAGE Branch Predictor

(2) Accurate Branch Prediction for Short Threads

Speculation and Prediction

(1) A Comparison of Full and Partial Predicated Execution Support for ILP Processors
(2) Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors

Speculation and Prediction

(1) Highly accurate data value prediction using hybrid predictors

(2) Focusing Procesor Policies via Critical-Path Prediction

Thread Level Speculation

(1) Multiscalar Processors

(2) A Scalable Approach to Thread-Level Speculation

Thread Level Speculation

(1) A Quantitative Assessment of Thread-Level Speculation Techniques

(2) Mitosis Compiler: An Infrastructure for Speculative Threading Based on Pre-Computation Slices

Midterm

Real Processors

(1) The Alpha 21264 Microprocessor

(2) The Microarchitecture of the Pentium 4 Processor

Helper Threads

(1) Execution-based Prediction Using Speculative Slices

(2) Dynamic Speculative Precomputation

Helper Threads

(1) An Event-Driven Multithreaded Dynamic Optimization Framework

(2) Design and Evaluation of Compiler Algorithms for Pre-Execution

Cache and Memory

(1) Improving Direct-Mapped Cache ... (Jouppi)
(2) Organization and Performance of a Two-Level ... (Wang, Baer, Levy)

Memorial Day

Cache and Memory

(1) Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching

(2) Putting the fill unit to work: dynamic optimizations for trace cache microprocessors

Fault-Tolerance

(1) DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design

(2) Transient Fault Detection via Simultaneous Multithreading

Fault-Tolerance

(1) Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor

(2) SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery

Power and Energy

(1) Selective CacheWays: On-Demand Cache Resource Allocation

(2) Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling

Power and Energy

(1) Reducing Power with Dynamic Critical Path Information

(2) Temperature-Aware Microarchitecture

Project Reports Due

June 13

Final Exam , 3-6 pm