Why CMPs?

The Case for a Single-Chip Multiprocessor by Kunle Olukotun, Basem A. Nayfeh, Lance Hammond, Ken Wilson and Kunyung Chang

Are Single-Chip Multiprocessors in Reach? A roundtable featuring commentary by Reinaldo Bergamaschi, Ivo Bolsens, Rajesh Gupta, Randolph Harr, Ahmed Jerraya, Kurt Keutzer, Kunle Olukotun and Kees Vissers. IEEE Design & Test of Computers, January-February 2001.

TLP Design Decisions by Chris Rijk. Ace's Hardware. November 28, 2004

Commercial CMPs

POWER4 System Microarchitecture. Tendler, Dodson, Fields, Le, Sinharoy, IBM Journal of Research and Development, January, 2002

April 13

Commercial CMPs

Network Processors. Two sets of slides (set1 and set2), courtesy of Laxmi Bhuyan

Introduction to the Cell Multiprocessor Kahle, Day, Hofstee, Johns, Maeurer, Shippy, IBM Journal of R&D, July, 2005.

CMP Design Space

Exploring the Design Space of Future CMPs - Huh, Keckler, Burger, PACT 2001

Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance, Rakesh Kumar, Dean M. Tullsen, Partha Ranganathan, Norman P. Jouppi, Keith I. Farkas, In 31st International Symposium on Computer Architecture, June, 2004.

CMP Design Space/Power

Power-Performance Considerations of Parallel Computing on Chip Multiprocessors  by Jian Li and Jose Martinez. Transactions on Architecture and Code Optimization. Volume 2, Number 4.December 2005.

Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction, Rakesh Kumar, Keith Farkas, Norm P. Jouppi, Partha Ranganathan, Dean M. Tullsen, In 36th International Symposium on Microarchitecture, December, 2003.

Extreme CMPs

Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture by Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen Kreckler and Charles Moore. ISCA-30. June 2003.

Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams by by M. B. Taylor, W. Lee, J. Miller, D. Wentzlaff, I. Bratt, B. Greenwald, H. Hoffmann, P. Johnson, J. Kim, J. Psota, A. Saraf, N. Shnidman, V. Strumpen, M. Frank, S. Amarasinghe and A. Agarwal, ISCA 2004.

Compiling for CMPs

Optimizing Compiler for a CELL Processor by A. Eichenberger, K. O'Brien, K. K. O'Brien, P. Wu, T. Chen, P. H. Oden, D. A. Prener, J. C. Shepherd, B. So, Z. Sura, A. Wang, T. Zhang, P. Zhao and M. Gschwind. PACT-2005. September 2005.

Optimizing Array-Intensive Applications for On-Chip Multiprocessors  by Ismail Kadayif, Mahmut Kandemir, Guilin Chen, Ozcan Ozturk, Mustafa Karakoy and Ugur Sezer. IEEE Transactions on Parallel and Distributed Systems. Vol 16, No. 5. May 2005.

Compiling for CMPs – Using Those Contexts

A Study of Source-Level Compiler Algorithms for Automatic Construction of Pre-Execution Code, Dongkeun Kim and Donald Yeung. ACM Transactions on Computer Systems. Vol. 22, No. 3. August 2004.

An Event-Driven Multithreaded Dynamic Optimization Framework, Weifeng Zhang, Brad Calder, and Dean M. Tullsen, In 2005 International Conference on Parallel Archtectures and Compilation Techniques, September, 2005.

Synchronization and Coherence

Fast Synchronization for Chip Multiprocessors by Jack Sampson, Ruben Gonzalez, Jean-Francois Collard, Norman Jouppi and Mike Schlansker. dasCMP '05 November 2005.

Exploiting Fine-Grain Thread Level Parallelism on the MIT Multi-ALU Processor, S.W. Keckler, W.J. Dally, D. Maskit, N.P. Carter, A. Chang, and W.S Lee. 25th Annual International Symposium on Computer Architecture (ISCA), July 1998

Synchronization and Coherence

Token Coherence: Decoupling Performance and Correctness,
Milo M. K. Martin, Mark D. Hill, and David A. Wood,
International Symposium on Computer Architecture (ISCA), June 2003.

Improving Multiple-CMP Systems Using Token Coherence  by Michael Marty, Jesse Bingham, Mark Hill, Alan Hu, Milo Martinand David Wood. HPCA-11. February 2005.

Synchronization and Coherence

M.P. Herlihy and J.E.B. Moss. Transactional Memory: architectural support for lock-free data structures. In Proceedings of the 1993 International Symposium on Computer Architecture, May 1993

Rajwar, Herlihy, Lai, Virtualizing Transactional Memory, ISCA 2005.

Synchronization and Coherence

Transactional Memory Coherence and Consistency, Lance Hammond, Vicky Wong, Mike Chen, Ben Hertzberg, Brian D. Carlstrom, John D. Davis, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis, and Kunle Olukotun, ISCA 2004

Characterization of TCC on Chip Multiprocessors by Austen McDonald, Jaewoong Chung, Hassan Chafi, Chi Cao Minh, Brian Carlstrom, Lance Hammond, Christos Kozyrakis and Kunle Olukotun. PACT-2005. September 2005.

Synchronization and Coherence

Token Coherence: Decoupling Performance and Correctness,
Milo M. K. Martin, Mark D. Hill, and David A. Wood,
International Symposium on Computer Architecture (ISCA), June 2003.

Improving Multiple-CMP Systems Using Token Coherence  by Michael Marty, Jesse Bingham, Mark Hill, Alan Hu, Milo Martinand David Wood. HPCA-11. February 2005.

Enhancing Single-thread Performance

Speculative Precomputation: Long-range Prefetching of Delinquent Loads, Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher Hughes, Yong-Fong Lee, Dan Lavery, John P. Shen, In 28th International Symposium on Computer Architecture, July, 2001

The potential for using thread-level data speculation to facilitate automatic parallelization
J.Gregory Steffan and Todd Mowry (Carnegie Mellon University)

Reliability for Chip Multiprocessors

BulletProof: A Defect-Tolerant CMP Switch Architecture. Kypros Constantinides, Stephen Plaza, Jason Blome, Bin Zhang, Valeria Bertacco, Scott Mahlke, Todd Austin, Michael Orshansky, In proceedings of the 12th International Symposium on High-Performance Computer Architecture (HPCA-12), February, 2006

Fingerprinting: Bounding Soft-Error Detection Latency and Bandwidth Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, and Andreas G. Nowatzyk International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XI), October 2004

More Compilation

Automatic Thread Extraction with Decoupled Software Pipelining Guilherme Ottoni, Ram Rangan, Adam Stoler, David I. August Princeton University, Micro 2005

An Event-Driven Multithreaded Dynamic Optimization Framework, Weifeng Zhang, Brad Calder, and Dean M. Tullsen, In 2005 International Conference on Parallel Archtectures and Compilation Techniques, September, 2005.

Interconnects

Interconnect-Aware Coherence Protocols for Chip Multiprocessors Liqun Cheng, University of Utah Naveen Muralimanohar, University of Utah Karthik Ramani, University of Utah Rajeev Balasubramonian, University of Utah John B. Carter, University of Utah, ISCA 2006

Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling, Rakesh Kumar, Victor Zyuban, Dean M. Tullsen, In 32nd International Symposium on Computer Architecture, June, 2005.

Other Potential Papers

Optimizing Replication, Communication, and Capacity Allocation in CMPs
 by Zeshan Chishti, Michael Powell and T. N. Vijaykumar. ISCA-32. June 2005.

A Chip Prototyping Substrate: The Flexible Architecture for Simulation and Testing (FAST)  by John D. Davis, Stephen E. Richardson and Kunle Olukotun. dasCMP '05. November 2005.

The Impact of Performance Asymmetry in Emerging Multicore Architectures Saisanthosh Balakrishnan, University of Wisconsin-Madison Ravi Rajwar, Intel Mike Upton, Intel Konrad Lai, Intel , ISCA 2005

Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors (slides) Michael Zhang, MIT Krste Asanovic, MIT, ISCA 2005

Multiple Instruction Stream Processor Richard A. Hankins, Intel Corp. Gautham N. Chinya, Intel Corp. Jamison D. Collins, Intel Corp. Perry H. Wang, Intel Corp. Ryan Rakvic, United States Naval Academy Hong Wang, Intel Corp. John P. Shen, Intel Corp.

An Integrated Framework for Dependable and Revivable Architecture Using Multicore Processors Weidong Shi, Georgia Tech Hsien-Hsin S. Lee, Georgia Tech Laura Falk, University of Michigan Mrinmoy Ghosh, Georgia Tech

Dynamic Helper Threaded Prefetching on the Sun UltraSPARC-CMP Processor Jiwei Lu, Abhinav Das, Wei-Chung Hsu, University of Minnesota Santosh G. Abraham, Khoa Nguyen, Sun Microsystems, Micro 2005

CMP Design Space Exploration Subject to Physical Constraints, Yingmin Li (University of Virginia), Benjamin Lee (Harvard University), David Brooks (Harvard University), Zhigang Hu (IBM T.J.Watson), Kevin Skadron (University of Virginia) , HPCA 2006

Mitigating Amdahl's Law Through EPI Throttling by Murali Annavaram, Ed Grochowski and John Shen. ISCA-32. June 2005.

Future Execution: A Hardware Technique for Prefetching in Chip Multiprocessors by Ilya Ganusov and Martin Burtscher. PACT-2005. September 2005.

Speculative Precomputation on Chip Multiprocessors by Jeffery A. Brown, Hong Wang, George Chrysos, Perry H. Wang and John P. Shen.