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Objective
In this lab, we will build a full-adder, a 4-bit adder from the full-adder, and
further a 16-bit adder from the 4-bit adder. Likewise, we will hierarchically
build a 2-input multiplexer, a
4-input multiplexer and a 16-input multiplexer.
We study the
functions and the delay of the logics. Use ONE worst case to demonstrate the delay on the critical path.
Note that in the lab,
we use FPGA Family: Virtex2, Device Type: XC2V80-5CS144.
Part 1. Tutorial
Go through the Xilinx ISE
6 In-Depth Tutorial (Chapter 3: Schematic-Based Design, Chapter 5: Design
Implementation, Chapter 6: Timing Simulation)
Write a
summary commenting on the overall process of using Xilinx and how to avoid
the possible mistakes in less than 100 words.
Part 2. Adders
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I.
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Build a full adder using Xilinx program.
Here is tutorial on how to build and simulate a full
adder in Xilinx. Simulate the behavior of the logic to verify the function. Use the
post-place&route simulation to demonstrate the worst delay of the circuit. Mark the amount of
the delay.
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II.
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Using the full adder built in I, build
a 4-bit adder & simulate the 4-bit adder.
Verify the function and demonstrate the worst delay of the circuit. Mark the amount of the delay.
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III.
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Using the 4-bit adder block built in
II, build a 16-bit adder & simulate the 16-bit adder. Verify the function and demonstrate the worst delay of the circuit. Mark the amount of
the delay.
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Part 3. Multiplexers
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I.
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Build
a circuit that translates a 4-bit parallel data to a serial output using
only 2:1 Muxes. Define the specification for this
4-bit parallel to serial circuit. (input, output & their relationship)
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II.
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Build & simulate the circuit. Verify the function and demonstrate the worst delay of the circuit. Mark the amount of
the delay.
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III.
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Using the 4:1 Mux block built in III,
build & simulate a 16:1 Mux. Verify the function and demonstrate the
worst delay of the circuit. Mark the amount of the delay. If you can't find a test bench to demonstrate the worst delay, explain why.
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Report
Title page:
- Names
of students and due date.
- Title
of the lab and objective.
- A brief
description of each person's contribution.
Content:
- Part
1 summary of overall process in Xilinx. (100 words or less!)
- Part
2: I, II, III (schematics diagram, behavior simulation diagram, timing report, post-place&route simulation diagram, as in tutorial).
- Part
3: I (function table), II (schematics diagram, behavior simulation diagram, timing report, post-place&route simulation diagram), III (chematics diagram, behavior simulation diagram, timing report, post-place&route simulation diagram, and explanation if necessary).
Grading
90% will be based on the completeness and
correctness of the report.
10% will be based on the neatness, organization, and following instruction of
the report format.
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