Multicore and GPU Programming: An Integrated Approach, by Gerassimos Barlas. Morgan Kaufmann, 2015. Chapter 6: § 6.3 (CUDA’s execution model, pp. 400-2); §6.7 (Optimization, pp. 432-442, 446-460).
Available electronically via the UCSD library at http://www.sciencedirect.com/science/book/9780124171374. UCSD Active Directory login required.
Hennessy and Patterson, Chapter 4, §4.4, pp 288-297, 304-308, “Graphical Processing Units”
Examine the PTX code within mm-shmem-coalesce in the CUDA Examples directory. This code also appears on pg. 112 of the Kirk and Hwu text.
To decipher this code, you’ll want to have this document nearby: Nvidia’s PTX ISA document
This blog is also helpful: stackoverflow.com/questions/16975727/confusion-with-cuda-ptx-code-and-register-memory
GPU Programming and Streaming Processors (Book chapter explains more details about the memory hierarchy)
Accelerated Computing Guide, Oak Ridge National Labortory. Nice overview about the GPU computing in general and the Kepler K20X in particular.
Barlas, §6.9-6.10. (Debugging and profiling)
Hennessy and Patterson, Chapter 4, §4.4, pp 298-300 “Nvidia GPU Instruction Set Architecture”