Pacheco. Chapter 2: pp. 29-34 (§ 2.3), p. 42 (latency and bandwidth).
John L. Hennessy and David A. Patterson, Computer Architecture, A Quantitative Approach, 5th Ed., Morgan Kaufmann, 2012, Chapter 7, §7.6 (pp. 648-653). [Available electronically via the UCSD library at http://site.ebrary.com/lib/ucsd/reader.action?docID=10509203. UCSD Active Directory login required.
John L. Hennessy and David A. Patterson, Computer Architecture, A Quantitative Approach, 5th Ed., Morgan Kaufmann, 2012, Chapter 5. [Available electronically via the UCSD library at http://site.ebrary.com/lib/ucsd/reader.action?docID=10509203. UCSD Active Directory login required. [An alternative to the graduate text.]
SSE Introduction. Short introduction
The Architecture of the Nehalem Processor Nehalem-EP SMP Platforms. This processor is newer than Bang’s CPUs, but most of the SSE discussions are relevant.
Wikipedia entries on Vectorization and Streaming SIMD Extensions
Automatic Intra-Register Vectorization for the Intel Architecture, A. Bik et al., Int. J. of Parallel Programming, 30(2):65-98 (2002). DOI