About Me


Atieh Lotfi


I ontained my Ph.D in computer science from University of California, San Diego. During my PhD, I supervised by Prof. Rajesh Gupta. I received my B.Sc. and M.Sc. in computer engineering from School of Electrical and Computer Engineering at University of Tehran . My current research is in the area of programmable hardware accelerators, computer architecture, compilers, and fault tolerant system design.

Curriculum Vitae

Publications

Accelerating Local Binary Pattern Networks with Software Programmable FPGAs
Jeng-Hau Lin*, Atieh Lotfi*, Vahideh Akhlaghi, Zhuowen Tu, Rajesh K. Gupta

DATE
2019

Low Overhead Tag Error Mitigation for GPU Architectures
Atieh Lotfi, Nirmal Saxena, Richard Bramley, Paul Racunas, Philip Shirvani

DSN
June 2018

ReHLS: Resource-Aware Program Transformation Workflow for High-Level Synthesis
Atieh Lotfi, Rajesh Gupta

ICCD
Nov 2017

Celerity: An Open-Source RISC-V Tiered Accelerator Fabric

HOTCHIPS
August 2017

RxRE: Throughput Optimization for High-Level Synthesis using Resource-Aware Regularity Extraction (Abstract Only)
Atieh Lotfi, Rajesh Gupta

FPGA
Feb 2017

GRATER: An Approximation Workflow for Exploiting Data-Level Parallelism in FPGA Acceleration
Atieh Lotfi, Abbas Rahimi, Amir Yazdanbakhsh, Hadi Esmaeilzadeh, Rajesh Gupta

DATE
March 2016

Aging-Aware Compilation for GPGPUs
Atieh Lotfi, Abbas Rahimi, Luca Benini, Rajesh Gupta

TACO
July 2015

SqueezCL: Squeezing OpenCL Kernels for Approximate Computing on Contemporary GPUs
Atieh Lotfi, Abbas Rahimi, Hadi Esmaeilzadeh, Rajesh Gupta

AC
Oct 2015

A Finegrain Distortion and Complexity Aware Parameter Tuning Model for the H.264/AVC Encoder
Mehdi Semsarzadeh, Atieh Lotfi, Mahmoud Reza Hashemi, Shervin Shirmohammadi

Sig. Proc.:
Image Com.

May 2013

Architectural Vulnerability Aware Checkpoint Placement in a Multicore Processor
Atieh Lotfi, Arash Bayat, Saeed Safari

IOLTS
June 2012

A Genetic-based Optimal Checkpoint Placement Strategy for Multicore Processors
Atieh Lotfi, Saeed Safari

CADS
May 2012

Configurable Architecture for Memory BIST
Atieh Lotfi, Parisa Kabiri, Zainalabedin Navabi

EWDTS
Sep 2011

Contact

Atieh Lotfi
alotfi [at] eng.ucsd.edu
Department of Computer Science and Engineering
University of California, San Diego
EBU3B Room 2150
9500 Gilman Drive, La Jolla, CA 92093-0404