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Journal Papers
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1.
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W. Rao, A. Orailoglu and R. Karri, "Towards
Nanoelectronics Processor Architectures", Journal of Electronic Testing: Theory and
Applications (JETTA), Special Issue
on Test, Defect Tolerance, and Reliability of Nanoscale Devices, in press, 2007
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2.
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W. Rao, A. Orailoglu and R. Karri, "Logic Mapping
in Crossbar based Nano Architectures", IEEE Design
& Test of Computers, Special Section on Computer-Aided Design for
Emerging Technologies, submitted, 2007
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Conference Papers
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1.
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W. Rao, A. Orailoglu and R. Karri, "Logic Level
Fault Tolerance Approaches Targeting Nanoelectronic PLAs", to appear in IEEE Design, Automation, and Test in
Europe, April 2007
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2.
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W. Rao, A. Orailoglu and R. Karri, "Topology
Aware Mapping of Logic Functions onto Nanowire-Based Crossbar Architectures", IEEE/ACM Design
Automation Conference, pages
723-726, July 2006
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3.
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W. Rao, A. Orailoglu and R. Karri, "Fault
Identification in Reconfigurable Carry Lookahead Adder Implementations
Targeting Nanoelectronic Fabrics", IEEE European
Test Symposium, pages 63-68, May 2006
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4.
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W. Rao, A. Orailoglu and R. Karri, "Nanofabric
Topoloties and Reconfiguration Algorithms to Support Dynamically Adaptive
Fault Tolerance", IEEE VLSI
Test Symposium, pages 214-219, April 2006
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5.
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W. Rao, A. Orailoglu and R. Karri, "Architecture-Level
Fault Tolerant Computation in Nanoelectronic Processors", IEEE International Conference on Computer
Design, pages 533-542, October
2005
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6.
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W. Rao, A. Orailoglu and R. Karri, "Fault
Tolerant Nanoelectronic Processor Architectures", IEEE Asia South Pacific Design Automation
Conference, pages
311-316, January 2005
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7.
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W. Rao, A. Orailoglu and G. Su, "Frugal
Linear Network-Based Test Decompression for Drastic Test Cost Reductions", IEEE International Conference on Computer
Aided Design, pages
721-725, November 2004
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8.
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W. Rao, A. Orailoglu and R. Karri, "Fault
Tolerant Arithmetic with Applications in Nanotechnology based Systems", IEEE International Test Conference, pages 472-478, October 2004
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9.
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W. Rao, I. Bayraktaroglu and A. Orailoglu,
"Test Application Time and Volume Compression through Seed Overlapping", IEEE/ACM Design Automation Conference, pages 732-737, June 2003
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10.
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W. Rao and A. Orailoglu, "Virtual Compression
through Test Vector Stitching for Scan Based Designs", IEEE Design,
Automation, and Test in Europe, pages 104-109, March 2003
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Workshop Papers
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1.
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W. Rao, A. Orailoglu and R. Karri, "Topology
Aware Mapping of Logic Functions onto Nanowire-based Crossbar Architectures", in the proceeding of the
2nd IEEE
International Workshop on Defect and Fault Tolerant Nanoscale Architectures
(NANOARCH) , June 2006
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2.
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W. Rao, A. Orailoglu and R. Karri, "Defect and
Fault Masking in Nanofabric through Redundancy Adaption", the 7th IEEE Latin-American
Test Workshop (LATW) , March 2006
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3.
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W. Rao, A. Orailoglu and R. Karri, "Architecture-level
Fault Tolerant Computation in Nanoelectronic Processors", in the proceeding of the
1st IEEE
International Workshop on Defect and Fault Tolerant Nanoscale Architectures
(NANOARCH) , May 2005
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4.
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W. Rao, A. Orailoglu, T. Wei, K. Wu and R. Karri, "Fault Tolerant Nanoscale
Architectures", the 6th
IEEE Latin-American Test Workshop (LATW) , March 2005
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