CSE 30 Midterm Review

Read, sign, and return your CSE30 Integrity of Scholarship Agreement BRING ID. You will be allowed to bring in an 8.5"x11" sheet of paper with one side filled in, handwritten. No calculators/electronic devices. Read Ch. 1 - 6 in textbook Review PA0, PA1, and PA2 Review Quizzes 1, 2, and 3 (and Sample Exercises) Compilation processes/phases cc -> cpp -> ccomp -> as -> ld -> exe (a.out) 5 areas of the C Runtime Environment Text, Data, BSS, Heap, Stack Powers of 2 226 = 220 * 26 = 1M * 64 = 64M 8K = 8 * 1K = 23 * 210 = 213 Concepts of classic sequential von Neumann machine (SISD) CPU, memory, I/O, bus[es] basic execution cycle: IF, ID, OF, EX, ST Logical view of CPU CU, Regs, ALU, internal bus[es] Stack Architecture push, pop, operations performed on operands on the stack Accumulator Architecture load, store, operations performed on ACC and operand Load/Store Architecture load, store, operations performed on operands in registers SPARC Architecture Data Types byte, halfword, word, single, double Big Endian vs. Little Endian ASCII (vs. EBCDIC) (vs. Unicode) Number Systems Base conversions (binary/octal/decimal/hexadecimal) Integer representations (signed/unsigned) Signed: sign magnitude/1's complement/2's complement BCD Binary addition with 2's complement subtraction as addition overflow detection condition code bits [N Z V C] SPARC Architecture Instruction Set Register sets (in, local, out, global) standard convention for their use passing paramters and return values special registers (%g0, %sp, %fp) Basic 3 operand instructions op regsrc1, regsrc2 or immediate constant, regdest Synthetic instructions and pseudo-ops set, mov, cmp, inc, ... Control and branch instructions call, bXX ("delayed control transfer") instructions which set condition code bits cmp, addcc (vs. add) branching logic using cmp branching logic using other ops (like addcc) signed branches, unsigned branches, condition code branches while, do-while, for loops if-then, if-then-else statements Pipelining 2 program counters (%pc and %npc) delay slot optimizations fill with instruction with no data dependency annulled branches counting down to zero vs. up to X Bit-wise operations Boolean logic and, or, xor, not [C operators (&, |, ^, ~)] xnor, andn, orn NAND, NOR Truth tables Logic gates Bit masks, bit operation identities Swap values without a temporary with xor tst, btst, bset, bclr, btog Bit shifts logical vs. arithmetic shift count range rotates Binary addition half adder full adder The Stack memory alignment restrictions for different data types save instruction and memory alignment of %sp sliding register set window caller's %sp -> new %fp in called register window set %sp (%o6) %fp (%i6) allocating space on the stack for local variables negative offset from %fp simple primitive data types (char, short, int, long) local variable internal alignment 1-d arrays, 2-d arrays, 3-d arrays storage map equations (a[i], a[i][j], a[i][j][k]) traversing with a ptr vs. array indexing structures structure padding/internal alignment unions ld and st instructions to access memory Subroutines Basics of parameter passing and return value convention %i0 / %o0 SPARC architecture features sliding register window in/local/out register sets call - ret save - restore calling conventions passing first 6 args in %o0-%o5 / %i0-%i5 preallocate 92 bytes (64 + 4 + 24) Open vs. Closed vs. Leaf Subroutines Rt.-Lt. Rule Operator Precedence Operator Associativity Order of Evaluation of Operands - 4 C operators that guarantee Lt. to Rt. evaluation of their operands lval / modifiable lval / rval The 4 C operators that evaluate to a modifiable lval