CSE 30 Final Review

One 8.5"x11" sheet of paper hand written using both sides. BRING ID No calculators. Read Ch. 1 - 14 in textbook Review all Programming Assignments C, SPARC Assembly, command line args, errno, functions used in PAs including perror(), strtol(), fopen(), fclose(), strtok(), qsort(), fgets(), printf(), fprintf(), strncpy()/memcpy(), strlen(), strchr(), malloc()/calloc()/realloc(), free(), getopt(), strcmp()/strncmp(), stat(), fread()/fwrite(), bsearch(), ... Review the Midterm and all Quizzes (and Sample Exercises) Everything from the Midterm Review material Stack/Local Variables 1-d arrays, 2-d arrays, 3-d arrays storage map equations (a[i], a[i][j], a[i][j][k]) traversing with a ptr vs. array indexing structures and unions structure padding/internal alignment Subroutines Open subroutines Closed subroutines Recursion! Stack Frames local variables system-specific bookkeeping parameters Typical CISC calling convention SPARC architecture features sliding register window in/local/out register sets call - ret save - restore calling conventions passing first 6 args; passing args 7+; preallocate 92 bytes (64 + 4 + 24) Leaf subroutines call - retl/nop No save - restore IEEE Floating Point Single precision / double precision Decimal fixed-point -> binary fixed-point -> normalization/hidden bit Sign bit | biased-127 exponent | mantissa/fraction Underflow/overflow/rounding/propagation errors FP arithmetic comparisions Text, Data, and Linkage Text/Data/BSS/Heap/Stack Relocatable linker (linkage editor) Static vs. dynamic linking Extern declarations Storage allocation locations Scope/visibility and Lifetime of variables/constants/functions in C Loader Thread safety and Static variables SPARC architecture Machine Instructions Simple instruction encoding and decoding Format 2, Branch instructions Format 3, 2nd source register instructions Format 3, Immediate constant instructions Given opcode/branch condition tables & register field mappings You need to know internal layout/format of instructions set vs. mov Exercises 8-1 & 8-2 (p. 244) Input/Output Big picture: external devices(disk) -> memory -> caches -> registers Fast CPU / Slow external devices Locality of Reference Caches Buffer cache Instruction cache Data cache L1/L2 caches write-through vs. write-back cache replacment policies Buffering Multilevel storage hierarchy Memory Mapped I/O / I/O Mapped / Dedicated I/O Processors Level of CPU Involvement Programmed I/O Interrupt Driven I/O DASD / SASD DMA burst-mode cycle-stealing Block Devices Disks - Cylinder Groups Seek time / Latency time / Transfer time Character Devices User <-> Supervisor mode Upper half / lower half of device driver synchronous vs. asynchronous access into the kernel Context Switching partial vs. full context switch Memory Management MMU Contexts/Regions/Segments/Pages Demand paging Page fault Page replacement policies Swapping Thrashing TLB Context Switching Traps PSR ALU, Control Unit, and Registers (Inside the CPU) Big picture ALU operations Combinational logic circuits Sequential logic circuits synchronous vs. asynchronous Tri-State devices Registers Control Unit operations hardwired vs. microprogrammed RISC vs. CISC Exploiting parallelism Other Architectures RISC vs. CISC vs. EPIC