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I am a PhD
graduated from
Department of Computer Science & Engineering,
University of California, San Diego. My advisor is
Professor C. K. Cheng. Here are
my
thesis and
defense. I'm interested in CAD algorithms and combinatorial optimization on VLSI systems, complexity of 3-D circuit design, low power bus architecture, and any other exciting future technologies. |
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Knapsack, a little game I developed
for iPhone or iPod Touch, with iPhone OS 2.2 or later. Based on the classic knapsack problem, the objective is simplified, and easy drag-and-drop operations are used on the iPhone touch screen. Getting started is easy, but the strategy may not be simple. Check it on App Store~ |
Selected Publications
| Physical Synthesis of Bus Matrix for High Bandwidth Low Power On-chip Communications |
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| Renshen Wang, Evangeline Young, Ronald Graham and Chung-Kuan Cheng. ACM International Symposium on Physical Design, March 14-17, 2010 | ||
| Low Power Gated Bus Synthesis using Shortest-Path Steiner Graph for System-on-Chip Communications |
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| Renshen Wang, Nan-Chi Chou, Bill Salefski and Chung-Kuan Cheng. ACM/IEEE Design Automation Conference, July 26-31, 2009 | ||
| On the Complexity of Graph Cuboidal Dual Problems for 3-D Floorplanning of Integrated Circuit Design |
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| Renshen Wang and Chung-Kuan Cheng. ACM Great Lakes Symposium on Very-large-scale Integration (GLSVLSI), May 10-12, 2009 | ||
| Octilinear Redistributive Layer Routing in Bump Arrays |
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| Symmetrical Buffer Placement in Clock Trees for Minimal Skew Immune to Global On-chip Variations |
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| Representing Topological Structures for 3-D Floorplanning |
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| Low Power Passive Equalizer Design for Computer Memory Links | ||
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| 3-D Floorplanning Using Labeled Tree and Dual Sequence | ||
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| Layer Minimization of Escape Routing in Area Array Packaging |
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| Campus Virtual Tour System Based on Cylindric Panorama | ||
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| Buffer Space Planning for Long Interconnections | ||
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| An Improved P-admissible Floorplan Representation Based on Corner Block List | ||
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Curriculum Vitae
Contact Info:
