• 1. Yenchuen Wei, “Circuit Partitioning and Its Applications to VLSI Designs,” CSE Dept., 6/14/1990.
  • 2. Robert Clinton Carden IV,“Microelectronics Global Routing and Feasibility Estimation Using a Multicommodity Flow Approach,” CSE Dept., 5/20/1991.
  • 3. Takeo Hamada,“Hierarchical Partitioning, Timing Driven Placement, and Wiring Estimation of Very Large Scale Integrated Systems”, CSE Dept., 5/28/1992.
  • 4. Chingwei Yeh,“Multiple-Way Partitioning and Clustering of VLSI Circuits”, ECE Dept.,5/28/1992.
  • 5. So-Zen Yao,“Microelectronics Layout Compaction and Design Verification”, CSE Dept.,1/15/1993.
  • 6. Nan-Chi Chou,“The Application of Hierarchical Trees to Circuit Partitioning, Clock Net Routing, and Connectivity Verification Problems”, CSE Dept.,9/14/93.
  • 7. Jiao Fan,“Computer Aided Design of Optoelectronic Multi-Chip Modules”, ECE Dept.,5/26/94.
  • 8. Lung-Tien Liu,“Performance Driven Partitioning using Retiming and Replication”, CSE Dept., 6/22/94.
  • 9. Robert Carragher, “Issues in Performance Driven Computer Aided Design”, CSE Dept., 8/30/94.
  • 10. Jae Chung,“High Performance Signal Distribution Algorithms and Applications for Very Large Scale Integrated Systems and Multichip Modules”, CSE Dept., 6/21/95.
  • 11. John Lillis,“Algorithms for Performance Driven Design of Integrated Circuits”, CSE Dept., 8/13/96.
  • 12. Ming-Ter Kuo,“Circuit Partitioning in Hierarchical Design”,CSE Dept., 10/28/96.
  • 13. De-Yu Kao, “VLSI Interconnect Synthesis”,ECE Dept., 1/26/98.
  • 14. Pei-Ning Guo, “Floorplan and Placement Approaches for VLSI Physical Design”,CSE Dept., 12/4/98.
  • 15. Frank Liu,“A Higher-Order Moment Model for Multiport Circuits”,CSE Dept., 12/4/98.
  • 16. Yingxin Pang,“A Floorplanning Algorithms for VLSI Physical Design Automation”,CSE Dept., 5/27/00.
  • 17. Xiao-Dong Yang,“A Reduced Order Modeling and Analysis for VLSI RLC Interconnect”,CSE Dept., 5/27/00.
  • 18. Zhanhai Qin,“A Topological Circuit Reduction: Theory and Applications”,CSE Dept., 8/1/03.
  • 19. Zhengyong Zhu,“Efficient Large-Scale Transistor-Level Transient Analysis”,CSE Dept., 6/7/05.
  • 20. Bo Yao,“Physical Planning of VLSI Layout”,CSE Dept., 8/2/05.
  • 21. Hongyu Chen,“On-Chip Interconnect Architectures: Perspectives of Layout, Circuits,and Systems”, CSE Dept., 9/26/05.
  • 22. Shuo Zhou,“Static Timing Analysis in VLSI Design”, CSE Dept., 4/18/06.
  • 23. Jianhua Liu,“Contemporary Data Path Design Optimization”, CSE Dept., 6/2/06.
  • 24. Yuanfang Hu,“On-Chip Interconnection Architecture Optimization Using a MulticommodityFlow Approach”, CSE Dept., 2/9/07.
  • 25. Haikun Zhu,“High Performance Low Power VLSI Designs”, CSE Dept., 3/22/07.
  • 26. Emel Yuceturk (Co-Chair), “Generalized Volterra Series Model for Highly Nonlinear Optical Interconnects, Circuits and Devices,” CSE Dept., 6/15/07.
  • 27. Rui Shi,“Off-Chip Wire Distribution and Signal Analysis”,CSE Dept., 5/23/08.
  • 28. Yi Zhu,“Interconnection Networks Synthesis and Optimization”,CSE Dept., 6/19/08.
  • 29. Ling Zhang,“Low Power High Performance Interconnect Design and Optimization”, CSE Dept., 11/20/08.
  • 30. Wanping Zhang,“Power Network Analysis and Optimization”,CSE Dept., 7/24/09.
  • 31. Renshen Wang,“Physical Planning to Embrace Interconnect Dominance in Power and Performance”,CSE Dept., 6/3/10.
  • 32. Yulei Zhang,“Design and Optimization of High-Performance Low-Power CMOS VLSI Interconnects”,ECE Dept., 6/1/11.
  • 33. Amirali Shayan,“System Level Design of Power Distribution Network for Mobile Computing Platforms”,CSE Dept., 9/9/11.
  • 34. Peng Du,“Power Network Verification and Optimization at Early Stages”,CSE Dept., 12/6/11.
  • 35. Xiang Hu,“Analysis of Microelectronic Power Distribution Networks and Exploring of 3D ICs”,ECE Dept., 5/30/12.
  • 36. Shih-Hung Weng, “Circuit Simulation via Matrix Exponential Method”,CSE Dept., 5/31/2013.
  • 37. Jingwei Lu, “Analytic VLSI Placement using Electrostatic Analogy”,CSE Dept., 12/5/2014.
  • 38. Yute Wang,“Developing a Pervasive Brain-Computer Interface System for Naturalistic Brain Dynamics”, CSE Dept., 4/15/2015.
  • 39. Hao Zhuang,“Exponential Time Integration for Transient Analysis of Large-Scale Circuits”, CSE Dept., 8/26/2016.
  • 40. Xiang Zhang, “Design, Analysis and Application of System-Level Power Distribution Network”, ECE Dept., 7/14/2017.
  • 41. Ilgweon Kang,“Floorplan Representation, Global Placement, and Routability Analysis for VLSI Layout Design Automation”, CSE Dept., 2/12/2018.
  • 42. Xinyuan Wang,“Advanced Integration Algorithms for VLSI Circuit Transient Simulation”,ECE Dept., 8/26/2020.
  • 43. Dongwon Park,“Logical Reasoning Techniques for Physical Layout in Deep Nanometer Technologies”, ECE Dept., 4/7/2021.
  • 44. Poya Hsu,“Computational Methodologies for Cardiac Signal Applications: Arrhythmia Classification, Biometric Identification, and Blood Pressure Estimation”, CSE Dept., 11/19/2021.
  • 45. Daeyeal Lee, “Logical Reasoning Techniques for VLSI Applications”, ECE Dept., 2022.
  • 46. Chiatung Mark Ho,“Novel Computer Aided Design (CAD) Methodology for Emerging Technologies to Fight the Stagnation of Moore's Law”, ECE Dept., 5/20/2022.
  • 47. Uday Mallappa,“AI for Design Optimization and Design for AI Acceleartion”, ECE Dept.,11/30/2022.
  • 48. Kuanjung Chiang,“EEG-Based Assessment of Human Cognitive and Affective States in Real-World Scenarios”, CSE Dept., 3/22/2023.
  • 49. Chester Holtz,“Constrained Graph Embedding with Applications to Chip Placement and Machine Learning”, CSE Dept., 5/8/2023.