I am a Distinguished Professor at the Department of Computer Science and
Engineering and an Adjunct Professor at the Department of Electrical and
Computer Engineering, the University of California, San Diego. I have served
as a Senior Engineer, and Consultant at various System,
Design, and Electronic Desgin Automation Companies. I got my Ph.D. from
the Department of Electrical Engineering and Computer Sciences at the University
of California, Berkeley in 1984.
Classic Works
Ratio Cut: We coined the term "Ratio Cut" for balanced partitioning via rational objective functions.
Y.C. Wei and C.K. Cheng, "Towards Efficient Hierarchical Designs by Ratio Cut Partitioning," IEEE Int. Conf. on Computer-Aided Design, pp. 298-301 Nov. 1989.
Cheng, C.K. and Hu, T.C., Ancestor tree for arbitrary multi-terminal cut functions. Annals of Operations Research, 33(3), pp.199-213, 1991,
Floorplan Representation: cited in The Art of Computer Programming, Volume 4B, D.E. Knuth, Addison Wesley, 2022.
Yao, B., Chen, H., Cheng, C.K. and Graham, R.,
Floorplan representations: Complexity and connections. ACM Transactions
on Design Automation of Electronic Systems (TODAES), 8(1), pp.55-80, 2003,
Paul Erdos Number 2: Co-authorship (15 papers) with Ronald Graham (Erdos Number 1) and (1 paper) with Fan Chung Graham (Erdos Number 1).
Impact
Floorplanning: O-tree, a leading block floorplanning in terms of computational complexity and quality of the results
Guo, P.N., Cheng, C.K. and Yoshimura, T., 1999, June. An O-tree representation of non-slicing floorplan and its applications. In Proceedings of the 36th annual ACM/IEEE Design Automation Conference (pp. 268-273).
Placement: ePlace, a flat analytic placement which was accelerated with GPU: DREAMPlace, and optimized via metaparameter tuning: AutoDMP at Nvidia, and implemented as
the basic framework for mixed mode placement by leading EDA companies.
Lu, J., Chen, P., Chang, C.C., Sha, L., Huang, D.J.H., Teng, C.C. and Cheng, C.K., 2015. ePlace: Electrostatics-based placement using fast fourier transform and Nesterov's method. ACM Transactions on Design Automation of Electronic Systems (TODAES), 20(2), pp.1-34.
Global Routing: A multicommodity formulation with an error bound which became a stanadard for practice.
Carden, R.C., Li, J. and Cheng, C.K., 1996. A global router with a theoretical bound on the optimal solution. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(2), pp.208-216.
Standard Cell Library Designs: A SAT framework for standard cell library design automation;
the co-optimization methodology has been adopted for digital library generation by prominent design houses.
We integrate and automate the logic, topology, placement, and routing for
cell generation to explore design/system technology co-optimization.
A set of tools has been released via Github.
Reunion with the first Ph.D. graduate,
Arthur Wei,
1/11/2023. The event reminds me of our joint work on Ratio Cuts
Lunch meeting
photo, while
serving as the director of MS program for the Department, assisted by a wonderful program manager, Nadyne (middle), and bidding farewell to a precious student, 3/20/2023.
2023 CSE Department, Masters Program
Award Ceremony,
6/9/2023.
Learn some life lessons from a legend of the field, Prof. R. Rivest,
together with Fullbright Visiting Scholar Prof. S. Sur-Kolay,
at UCSD Faculty Club, 2/18/2026.
C.-K. Cheng, A. B. Kahng, B. Lin, Y. Wang, and D. Yoon, "An Extended Study of Gear-Ratio-Aware Standard Cell Layout Generation for DTCO Exploration," arXiv preprint arXiv:2603.13665, 2026.
B. Kang, A. Mischenko, M. Fujia, B. Lin, and C.K. Cheng,
"L2L: Logic to Layout Exploration of Standard Cell Library Design,"
ACM/IEEE Design Automation Conf. 2026.
Honors and Awards
NCR Best Teaching Award, School of Engineering, University of California,
San Diego, 1991.
Best Paper Awards, IEEE Circuits and Systems Society, CAD Transactions, 1997, and 2002.
IEEE Fellow, 2000.
IBM Faculty Awards, 2004, 2006, and 2007.
Honorary Appointment as a Guest Professor of the Department of
Computer Science & Technology, Tsinghua University, 2002-2008.
Runner Up of Best Poster Award, Research Expo, School of Engineering, UCSD,
L. Zhang, High Performance Current-Mode Differential Logic,
out of 51 posters in Computer Science and Engineering Dept.,
Feb. 23, 2007.
Best Poster Award, Research Expo, School of Engineering, UCSD,
A. Shayan-Arani, X. Hu, Power Distribution Design for 3D Integration,
out of 60 posters in Computer Science and Engineering Dept, Feb. 19, 2009.
Distinguished Faculty Award, UC San Diego, 2013.
Distinguished Professor, UC San Diego, 2014.
Cadence Academic Collaboration Award, 2016.
ACM/IEEE ASPDAC Prolific Author Award, 2020.
ACM/IEEE ASPDAC Best Paper Award, 2022.
ACM/IEEE ISPD Best Paper Award Candidate, 2023.
Lifetime Achievement Award, ACM Int. Conf. on Physical Design, 2027.
Services
Program Co-Chair, Int. Conf. on ASIC, ASICON, Oct. 2003.
Program Co-Chair, IEEE ASPDAC 2004.
Tutorial Co-Chair, IEEE ASPDAC 2005.
President 2003-2005, San Diego Chinese American Science and Engineering Association.
Tutorial Co-Chair, IEEE ASPDAC 2006.
One Day Tutorial Co-Organizer, ACM/IEEE DAC 2006.
Co-Chair, EDA Program, ICCCAS 2009.
General Chair, ACM/IEEE SLIP 2009.
UCSD Academic Senate Committee on Faculty Welfare (Member, Chair, 2015-2018)
IEEE Transactions on Computer-Aided Design, Associate Editor, 2020-2024
ACM ISPD 2011 Talk in Commemoration of Ernest S. Kuh
Distinguished Professor
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