| E-mail: |
jbrown at see-ess dot you-see-ess-dee dot ee-dee-you GNUPG key |
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| Ex-where: |
Architecture Lab CSE Building (aka EBU3B) Rooms 3250, 3252, and 3258 (No lab phone; send e-mail instead) |
| Publications: | See my publications page. |
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September 2010: I now work for Google (Google) in Mountain View.
"De-fense!": On April 20th 2010, I presented and successfully defended my dissertation, titled "Architectural Support for Efficient On-Chip Parallel Execution". The following five folks form the committee which oversaw this work; they are awesome and I'm extremely grateful to each for donating their valuable time to help me:
(older stuff)
My research area is processor architecture. My current research is focused on altering core design to more efficiently utilize chip-wide resources — in both under- and over-subscribed execution — and accelerating coherence for more conventionally designed chip multiprocessors.
Research areas I've worked in include: speculative and non-speculative automated multi-threading of applications for SMT and CMP processors, improving memory throughput for multi-threaded workloads, and hardware-assisted low-cost software prefetching.
Practically speaking, I spend an inordinate amount of time working on the SMTSIM and RSIM processor simulators, implementing research ideas and performing experiments. I've done a lot of additional development on SMTSIM as well; feature additions include additional platform support, multi-core hybrid SMT/CMP simulation, a basic memory coherence model, a trace cache and fill unit, a flexible configuration system that is almost entirely dynamic (not frozen at compile-time), as well as thread suspend/restart/migration capabilities.
I've interned twice at Intel and once at Bell Labs (Lucent Tech in Murray Hill NJ), I was an NSF Graduate Research Fellow for 2001 - 2003, and I've also taught two upper-division CSE courses at UCSD: the undergraduate Introduction to Computer Architecture, and the associated Project in Computer Architecture.
