CS 3220: Processor Design with FPGAs (Fall 2016)


Instructor: Hadi Esmaeilzadeh


Email: hadi [AT] cc [DOT] gatech [DOT] edu
Office: KACB 2336
Office hours: 4:30pm - 6:00pm Mon
Location: MRDC 2407
Class time: 3:05pm - 4:25pm MW

TAs:  Jongse Park (jspark [AT] gatech [DOT] edu). OH: 4:30pm - 6:00pm Mon
         Sufyan Dawoodjee (sufyan [AT] gatech [DOT] edu). OH: 4:30pm - 6:00pm Thu
         Office Hours held in KACB 2335.



Tentative Schedule (Subject to Change)


Week
Date
Topics Notes
1
8/22
No Class

8/24
Approximation and Specialization, Preassessment Test Lecture
2
8/29
Number Representation, Boolean logic Lecture
Assignment 0
8/31
Introduction to RTL Verilog
Solution quiz 0
Student group requests due
3
9/5
Official School Holiday - Labor Day

9/7
Verilog Test Harnesses and Simulation Tools Demo Class Notes (Navabi)
4
9/12
State Machines and Memories in Verilog Class Notes (Navabi)
9/14
Board Demo
Tool instalation due
5
9/19
Project ISA and Assembler
Assignment 1 Released
Lecture
project2-description.pdf
9/21
Project ISA and Assembler (II)

6
9/26
Clocks and PLL
Lecture
9/28
Session for Project 1

7
10/3
Single Cycle Processor
Lecture
Project 2 Released
10/5
Memory and Debugging

8
10/10
Official School Holiday - Fall recess

10/12
Pipelining
Lecture
9
10/17
Project 2 Help Session Lecture
10/19
Exception Handling and Protected Mode Support  Project 2 Due
10
10/24
Timers and I/O Devices 
10/26
Midterm 
11
10/31
Review of Midterm Solutions Assignment 3 Released
11/2
2-Stage Pipelining

12
11/7
Branch Prediction
Lecture
11/9
Devices and Bus
Lecture
Project 3 Due
Project 4 Released
13
11/14
Project 3 Demo

11/16
No Class

14
11/21
Interrupts
Project 4 Due
Project 5 Released
11/23
Official School Break - Thanks giving

15
11/28
Project 4 Demo

11/30
Five-stage Pipeline Processor and Acceleration Lecture
16
12/5
Neural Processing Units Lecture
12/7
Final Exam Review Project 5 Due
17
12/9
Final Exam