CS 3220: Processor Design with FPGAs (Fall 2016)

Instructor: Hadi Esmaeilzadeh

Email: hadi [AT] cc [DOT] gatech [DOT] edu

Office: KACB 2336

Office hours: 4:30pm - 6:00pm Mon

Location: MRDC 2407

Class time: 3:05pm - 4:25pm MW

TAs: Jongse Park (jspark [AT] gatech [DOT] edu). OH: 4:30pm - 6:00pm Mon
Sufyan Dawoodjee (sufyan [AT] gatech [DOT] edu). OH: 4:30pm - 6:00pm Thu
Office Hours held in KACB 2335.

Resources

Quick Start Guide, by Jongse Park.
Example Verilog Codes
SignalTap II with Verilog Designs
Memory Initialization File (.mif) overview
How to reinitialize MIF file wihtout recompiling on Quartus
Debouncing switches

Verilog:

An Introduction to Verilog, by Andrew Tuline.
Verilog HDL Quick Reference Card, by QUALIS.
Quick Reference for Verilog HDL, by Rajeev Madhavan, AMBIT Design Systems, Inc.
Verilog HDL Quick Reference Guide, by Stuart Sutherland, SUTHERLAND HDL.

Modelsim:

Modelsim Tutorial, by Mentor Graphic.
Modelsim Quick Guide, by Mentor Graphic.
Modelsim Users Manual, by Mentor Graphic.
Modelsim Reference Manual, by Mentor Graphic.