Rajesh Gupta

Rajesh Gupta is a professor and holder of the QUALCOMM endowed chair in Embedded Microsystems in the Department of Computer Science & Engineering at UC San Diego, California. He received his B. Tech. in Electrical Engineering from IIT Kanpur, India in 1984, MS in EECS from UC Berkeley in 1986 and a Ph. D. in Electrical Engineering from Stanford University in 1994. Earlier he worked as a circuit designer at Intel Corporation, Santa Clara, California as a member of three successful processor design teams; and on the Computer Science faculty at University of Illinois, Urbana-Champaign and UC Irvine. His current research is focused on energy efficient and mobile computing issues in embedded systems. He is author/co-author of over 150 articles on various aspects of embedded systems and design automation and four patents on PLL design, data-path synthesis and system-on-chip modeling. Gupta is a recipient of the Chancellor's Fellow at UC Irvine, UCI Chancellor's Award for excellence in undergraduate research, National Science Foundation CAREER Award, two Departmental Achievement Awards and a Components Research Team Award at Intel. Gupta served as founding Chair of the ACM/IEEE Conference on Models and Methods in Codesign (MEMOCODE) and founding Co-Chair of ACM/IEEE/IFIP Conference on Codesign and System Synthesis (CODES+ISSS). Gupta is editor-in-chief of IEEE Design & Test of Computers and serves on the editorial boards of IEEE Transactions on CAD and IEEE Transactions on Mobile Computing. He serves as the VP of Publications of the IEEE Council on Electronic Design Automation (CEDA). Gupta is a Fellow of the IEEE and a distinguished lecturer for the ACM/SIGDA and the IEEE CAS Society.

Gupta serves as an advisor to Tallwood Venture Capital, RealIntent, Calypto and Packet Digital Corporation.

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Research Interests:

Algorithms for VLSI design automation.
CAD for embedded and portable systems.
Computer architecture and organization.
VLSI design at various levels of abstractions.

Patents:

US 4,985,640: PLL Clock Generator Circuit
US 6,148,433: Regularity Extraction for Datapath Synthesis
US 6,152,612: IC/System Modeling using C++
US 6,594,808: Structural Regularity Extraction and Floorplanning in Datapath Circuits

For publications, please check out the group webpage.

Panels, Tutorials and Short Courses

``Design Tools and IC Design for On-Chip Wireless Systems,'' (with M. Srivastava) ICCAD , Santa Clara, CA, November, 1997.
``System Design using IC Cores: Design, Test and Sign-Off'', (with R. Haddad and R. Roy) DAC, Anaheim, CA, June 1997.
``Hardware-Software Co-design: Tools for Architecting Systems-On-A-Chip,''ASP-DAC, Makuhari, Japan, January, 1997.
``Recent Developments in Hardware-Software Co-design: Embedded System Synthesis and Optimization,'' (with P. Subramanya) VLSI Design, Hyderabad, India, January 1997.
``Computer-Aided Design for Embedded Sytems,'' ISCAS, Atlanta, May 1996.
``Panel: Opportunities and pitfalls in HDL-based IC Design,'' ICCD, Austin, October 1996.
``Hardware-Software Co-design for Embedded Systems,'' VLSI Design, Bangalore, India, January 1996.
``Panel: Future of System-level CAD,'' ISCAS, Atlanta, May 1996.
``CAD for Digital Embedded Systems,'' (with P. Koopman, A. Wolfe) DAC, San Francisco, June 1995.

Updated July 2002.

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