Garo Bournoutian

E-mail:

Research Area(s): Computer architecture, embedded/mobile system design, enhanced compiler-hardware interaction, application-specific hardware reconfiguration, and low-power mobile processor design.

Education:

• Ph.D. in Computer Engineering. University of California, San Diego. 2007 - 2014.
• M.S. in Computer Science. University of California, San Diego. 2005 - 2007.
• B.S. in Computer Engineering. University of California, San Diego. 2000 - 2005.
• B.S. in Cognitive Neuroscience. University of California, San Diego. 2000 - 2005.

Teaching:

• CSE 131 - Compiler Construction. Fall 2015, Spring 2015, Winter 2015, Fall 2014, Fall 2013, Summer 2011

Journal Publications:

• G. Bournoutian and A. Orailoglu, "Application-Aware Adaptive Cache Architecture for Power-Sensitive Mobile Processors," ACM Transactions on Embedded Computing (ACM TECS), pp. 41:1-41:26, 2013.
  DOI 10.1145/2539036.2539037
  [ ACM Library ] [ pdf ]
• G. Bournoutian and A. Orailoglu, "Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions," Design Automation for Embedded Systems (DAFES), pp. 309-326, 2010.
  [ DOI 10.1007/s10617-010-9058-y ] [ pdf ]

Conference Publications:

• G. Bournoutian and A. Orailoglu, "Mobile Ecosystem Driven Application-Specific Low-Power Control Microarchitecture" Proc. of the Int'l Conference on Computer Design (ICCD), pp. 764-771, 2015.
  [ pdf ]
• G. Bournoutian and A. Orailoglu, "Mobile Ecosystem Driven Dynamic Pipeline Adaptation for Low Power" Proc. of the Int'l Conference on Architecture of Computer Systems (ARCS), pp. 83-95, 2015.
  [ DOI 10.1007/978-3-319-16086-3_7 ] [ pdf ]
• G. Bournoutian and A. Orailoglu, "On-Device Objective-C Application Optimization Framework for High-Performance Mobile Processors" Proc. of the Int'l Conference on Design, Automation, and Test in Europe (DATE), pp. 430-436, 2014.
  [ ACM Library ] [ pdf ]
• G. Bournoutian and A. Orailoglu, "Dynamic Transient Fault Detection and Recovery for Embedded Processor Datapaths" Proc. of the Int'l Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), pp. 43-52, 2012.
  [ ACM Library ] [ pdf ]
• G. Bournoutian and A. Orailoglu, "Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors" Proc. of the Int'l Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), pp. 89-98, 2011.
  [ ACM Library ] [ pdf ]
• G. Bournoutian and A. Orailoglu, "Dynamic, non-linear cache architecture for power-sensitive mobile processors" Proc. of the Int'l Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS), pp. 187-194, 2010.
  [ ACM Library ] [ pdf ]
• G. Bournoutian and A. Orailoglu, "Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions," Proc. of the Int'l Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pp. 117-126, 2009. (Best Paper Candidate)
  [ ACM Library ] [ pdf ]
• G. Bournoutian and A. Orailoglu, "Miss reduction in embedded processors through dynamic, power-friendly cache design," Proc. of the 45th Design Automation Conference (DAC), pp. 304-309, 2008.
  [ ACM Library ] [ pdf ]

Recommendation Letters:

• If you are going to ask me to write a recommendation letter for you, please talk to me well in advance about it. I won't agree to write a letter unless it can be a strong letter. If I do agree, you will need to provide me with all the necessary materials at least a month before the letter is due. You should include your resume/CV, a copy of your academic transcript, scores on GRE or other relevant exams, descriptions of all the programs you are applying to and any forms they require me to use, deadlines for the letters, and any additional information about yourself (e.g., research lab experience, internships, a web site with a portfolio of your work, etc.) that would help me to write a strong letter.