CURRICULUM VITAE

FREDERIC DOUCET

8222 Regents Rd, #201
San Diego, CA 92122
(858) 558-8982
email: fdoucet (put @ here) ucsd (put dot here) edu
Canadian citizen

RESEARCH INTERESTS

• Design science, system level design, CAD for VLSI and SLD design, software engineering
• High-level design methodologies and tools for large scale system designs
• Management and leadership

EDUCATION

• now- PhD Student, Computer Science
  University of California, San Diego
  Current research: BALBOA CAD framework for high-level modeling.
• 2002, Master of Science, Computer Science
  University of California, Irvine
  Topic: CAD framework for high-level modeling of embedded computer systems
• 1999, Bachelor of Engineering, Computer Engineering
  École Polytechnique de Montréal
  Senior thesis topic: Compiler framework for C synthesis

AWARDS/RECOGNITION

• Semiconductor Research Corporation (SRC)
  Doctoral graduate fellowship, 2001-2006
• Fond pour la Formation de Chercheurs et l'Aide à la Recherche du Quebec (FCAR)
  Doctoral graduate scholarship, 2001-2003
• Natural Sciences and Engineering Research Council of Canada (NSERC)
  Postgraduate scholarship A, valid in a canadian university, 1999
• Inter-University Centre in Computer Architecture and VLSI
  Undergraduate research financial support, 05/98 - 09/98

PUBLICATIONS

F. Doucet, S. Shukla, M. Otsuka and R. Gupta
Balboa: A Component-Based Design Environment for System Models
To Appear in IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Dec. 2003

F. Doucet, S. Shukla and R. Gupta,
Typing Abstractions and Management in a Component Framework,
In Proc. of Asia and South Pacific Design Automation Conference, 2003

R. Gupta, S. Shukla and F. Doucet
Structured Composition Techniques for Embedded Systems,
In Proc. of International Conference on High Performance Computing, 2002

F. Doucet, M. Otsuka, S. Shukla and R. Gupta,
An Environment for Dynamic Component Composition for Efficient Co-Design,
In Proc. Design Automation and Test in Europe, 2002

F. Doucet, R. Gupta, M. Otsuka, P. Schaumont and S. Shukla,
Interoperability as a Design Issue in C++ Based Modeling Environment,
In Proc. International Symposium on System Synthesis, 2001

F. Doucet, M. Otsuka, R. Gupta and S. Shukla,
Efficient System Level Co-Design Environment using Split Level Programming,
Technical Report 01-34, CECS/UCI, July 2001

F. Doucet, V. Sinha and R. Gupta,
Structural Design Composition for C++ Hardware Models,
In Proc. CS VLSI Workshop, 2001

F. Doucet, V. Sinha, R. K. Gupta,
Microelectronic System-on-Chip Modeling using Objects and their Relationships,
In Proc. 1st Online Symposium for Electrical Engineers, 2000

V. Sinha, F. Doucet, C. Siska, R. K. Gupta, S. Liao, A. Ghosh,
YAML: A Tool for Hardware Design Visualization and Capture,
In Proc. International Symposium on System Synthesis, 2000

F. Doucet R. K. Gupta,
Debugging of Polymorphic SystemC C++ Code for Hardware Design,
Technical Report 00-06, Center for Embedded Computer Systems,
University of California at Irvine, February 2000

F. Doucet, V. Sinha, C. Siska, R. K. Gupta,
System-on-Chip Modeling using Objects and their Relationships,
Technical Report 99-53, University of California at Irvine,
October 1999

WORK EXPERIENCE

• CAD Engineer (intern), Conexant Systems Inc, Newport Beach, Calif., 06/03-09/03
  Core Engineering
  Research on communication and protocol modeling for system-on-chips

• CAD Engineer (intern), Intel Corporation, Santa Clara, Calif., 06/00-09/00
  Enterprise Processor Division: design methodology (EPD-DM)
  High-level modeling for microprocessor distributed
  memory in C++, worked on design and methodology research,
  built prototypes and test environment

• Research Assistant, University of California, Irvine, 08/99-
  Center for Embedded Computer Systems (CECS)
  High level hardware design using C++.
  Investigation on simulation and synthesis and compiler issues

• Research Assistant, École Polytechnique de Montréal, 6/98-08/99
  Microelectronics Research Group
  Investigated architectures, compilers and design methodology
  for high throughput-data intensive video applications.
  Built a data flow analysis framework and a C to VHDL
  translator in the SUIF compiler framework.

• Teacher Assistant, École Polytechnique de Montréal, 1/98-04/99
  Electrical and Computer Engineering Departement
  Introduction to Microprocessors Lab:
  embedded systems design and project management

• Software Engineer (intern), Lockheed Martin Canada, Montreal, 1/97 - 8/97
  Operation Room Tactical Training Divison
  Analysis, design and implementation a distributed computing
  framework similar to CORBA, and of various reusable software
  components for a Canadian Navy frigates operation room
  training system.

• Software Engineer (intern), Ranmar Business Systems, Montreal, 5/96 - 8/96
  Analysis, design and implementation of various software
  components for insurance brokerage software systems.

TECHNICAL KNOWLEDGE

• System level design: CAD tools, methodology and management
• Software engineering: building CAD tools and environments, methodology, management,
  object-oriented design, compilers, UML, C++, Java, Unix and Windows.
• Hardware engineering: VLSI design, behavioral and structural synthesis.
  Experience with VHDL, SystemC, Cynlib, SpecC and related tools.

RELEVANT ACTIVITIES

Student Member ACM (SIGDA) and IEEE (CS/CAS)

Paper referee for IEEE TCAD, DAC, ICCAD, DATE, CODES

References available on request