Research Project Abstracts and Related Publications

1) Simulate & Eliminate: A Top-to-Bottom Design Methodology for Application-Specific Multi-Core Architectures:
Integrated circuit technology will continue to follow Moore's Law for the foreseeable future, and multi-core architectures will provide a means to increase performance while keeping power consumption under control. There is also an increasing trend towards application-specific multi-core processing, particularly in embedded computing devices that have stringent area, performance and power consumption requirements. These application-specific
multi-core architectures are carefully tuned for a particular application, therefore consuming less area and power while achieving high performance compared to their equivalent general-purpose implementations. However, achieving the desired constraints requires careful tuning of the underlying architecture with a significant amount of time and effort.

Therefore, a high level design tool for design space exploration and fast prototyping of applicationspecific multi-core architectures is essential. We are currently developing a tool, Simulate & Eliminate (S&E), which produces synthesizable hardware description language (HDL) for application-specific multi-core architectures for given particular application(s). S&E follows a top-to-bottom approach by first generating a general-purpose multi-core architecture. Then, the provided applications are simulated on this architecture and the unneeded functionality (interconnect, functional resources, control and memory) is eliminated resulting in application-specific multi-core architecture. Our approach is distinct from the common approach of synthesis of microarchitecture datapaths from primitives. The existing tools employ a bottom-to-top methodology, which pieces together functional units, interconnect and control logic based on the given application. The technical advantages of S&E's top-to-bottom design methodology are scalability, reconfigurability and ease of design. This project is patented at UCSD and currently funded by Intel Corporation.

  • [ACM TECS] GUSTO: An Automatic Generation and Optimization Tool for Matrix Inversion Architectures, Ali Irturk, Bridget Benson, Shahnam Mirzaei and Ryan Kastner, ACM Transactions on Embedded Computing Systems.
  • [TCAD] Simulate and Eliminate: A Methodology to Design Application Specific Multi-Core Architectures for Matrix Computations, Ali Irturk, Janarbek Matai, Jason Oberg, Jeffrey Su and Ryan Kastner, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
  • [FCCM] Design and Implementation of an FPGA-based Real-Time Face Recognition System, Janarbek Matay, Ali Irturk, Ryan Kastner, 19th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011).
  • [DAC] Xquasher: A Tool for Efficient Computation of Multiple Linear Expressions, Arash Arfaee, Ali Irturk, Nikolay Laptev, Ryan Kastner, Farzan Fallah, Design Automation Conference (DAC 2009).
  • [WCNC] Architectural Optimization of Decomposition Algorithms for Wireless Communication Systems, Ali Irturk, Bridget Benson, Nikolay Laptev and Ryan Kastner, IEEE Wireless Communications and Networking Conference (WCNC 2009), April 2009.
  • [RAW] Energy Benefits of Reconfigurable Hardware for use in Underwater Sensor Nets, Bridget Benson, Ali Irturk, Junguk Cho, Ryan Kastner, 16th Reconfigurable Architectures Workshop (RAW 2009), May 2009.
  • [WHPCF at SC] FPGA Acceleration of Mean Variance Framework for Optimum Asset Allocation, Ali Irturk, Bridget Benson, Nikolay Laptev and Ryan Kastner, Workshop on High Performance Computational Finance at SC08 International Conference for High Performance Computing, Networking, Storage and Analysis, November 2008.
  • [ICFPT] Automatic Generation of Decomposition based Matrix Inversion Architectures, Ali Irturk, Bridget Benson and Ryan Kastner, IEEE International Conference on Field-Programmable Technology (ICFPT), December 2009.
  • [SASP] An FPGA Design Space Exploration Tool for Matrix Inversion Architectures, Ali Irturk, Bridget Benson, Shahnam Mirzaei and Ryan Kastner, IEEE Symposium on Application Specific Processors (SASP), June 2008.
  • [WUWNet] Survey of Hardware Platforms for an Energy Efficient Implementation of Matching Pursuits Algorithm for Shallow Water Networks, Bridget Benson, Ali Irturk, Junguk Cho, and Ryan Kastner, Third ACM International Workshop on UnderWater Networks (WUWNet), in conjunction with ACM MobiCom 2008, September 2008.
  • [ASAP] Design Space Exploration of a Cooperative MIMO Receiver for Reconfigurable Architectures, Shahnam Mirzaei, Ali Irturk, Ryan Kastner, Brad T. Weals and Richard E. Cagley, IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 2008.
  • [THESIS] GUSTO: General architecture design Utility and Synthesis Tool for Optimization, Ali Irturk, PhD Thesis, Department of Computer Science and Engineering, University of California, San Diego, September 2009.
  • [THESIS] Implementation of QR Decomposition Algorithms using FPGAs, Ali Irturk, MS Thesis, Department of Electrical and Computer Engineering, University of California, Santa Barbara, June 2007.
  • [TECH REP] An Optimization Methodology for Matrix Computation Architectures, Ali Irturk, Bridget Benson, and Ryan Kastner, UCSD Technical Report, CS2009-0936.
  • [TECH REP] FPGA Implementation of Adaptive Weight Calculation Core Using QRD-RLS Algorithm, Ali Irturk, Shahnam Mirzaei and Ryan Kastner, UCSD Technical Report, CS2009-0937.
  • [TECH REP] An Efficient FPGA Implementation of Scalable Matrix Inversion Core using QR Decomposition, Ali Irturk, Shahnam Mirzaei and Ryan Kastner, UCSD Technical Report, CS2009-0938.
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2) Hardware Security: High assurance systems such as those found in flight control and banking systems require strict guarantees on correct operation or they face catastrophic consequences. Ensuring that these systems operate as intended is an extremely difficult and costly problem. Some have estimated that such assurance can cost $10K per line of code and take up to 10 years. To realize high assurance systems, we are working on two different topics: 1) Gate-Level Information-Flow Tracking (GLIFT) logic to guarantee non-interference and 2) exploitation of 3D integrated circuit technology to secure COTS hardware.

Currently, we are exploring gate-level information-flow tracking (GLIFT) to guarantee non-interference. Noninterference is a common property that often needs to be guaranteed in high assurance systems where certain parts of the system should never interfere with other parts. For example, the Boeing 787 aircraft has connectivity between the user and light control networks. Ensuring that there are no unintended information flows between the two networks is critical for the correct operation of the aircraft.

We are also developing novel security management techniques built around fundamentally new hardware abilities enabled by 3-D integration. Manufacturers are often forced to choose less costly alternatives, such as an older, cheaper process increasing the gap in performance between low volume high assurance systems and commercial systems every year. As a result of these economic factors, designers of trustworthy systems requiring high performance need some way to incorporate commercial hardware components without compromising security. Therefore a method of bridging the gap between cutting-edge technology and trustworthy systems is of paramount necessity. Our work shows that commodity integrated circuits could be enhanced with a separate silicon layer, stacked using 3-D integration, therefore enabling different ways of introspection. This Project is funded by National Science Foundation.

  • [IWLS] An Improved Encoding Technique for Gate Level Information Flow Tracking, Wei Hu, Jason Oberg, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Dejun Mu, and Ryan Kastner, The International Workshop on Logic and Synthesis.
  • [ERSA] Enforcing Information Flow Guarantees in Reconfigurable Systems with Mix-Trusted IP, Ryan Kastner, Jason Oberg, Wei Hu, Ali Irturk Invited Paper, The International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA).
  • [TCAD] Theoretical Fundamentals of Gate Level Information Flow Tracking, Wei Hu, Jason Oberg, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Ryan Kastner, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
  • [DAC] Information Flow Isolation in I2C and USB, Jason Oberg, Wei Hu, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Ryan Kastner, Design Automation Conference (DAC 2011).
  • [DAC] Theoretical Analysis of Gate Level Information Flow Tracking, Jason Oberg, Wei Hu, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Ryan Kastner, Design Automation Conference (DAC 2010).

3) Accelerating Biomedical Imaging: I am also working on a number of projects related to accelerating biomedical imaging. These include optical mapping of heart tissue, stem cell identification and selection, and inertial microfluidics. All of these applications are for the most part, currently done in a tedious, non-optimized manner, and involve hours/days of time for manual computation. Automation of these techniques could have profound effects on experiments, treatments and therapies for ailments ranging from heart disease to cancer. These projects involve understanding the algorithm and translating onto a computation device (Graphic Processing Unit, Field-Programmable Gate Array, Multi-Core Processor) with the aim of creating a real-time implementation.

As an example, one of my current projects brings together researchers from the medicine, bioengineering, and computer science departments to develop an experimental tool that has the potential for wide usage in cardiac research. This project investigates the Graphic Processing Unit (GPU) acceleration of optical mapping algorithm for cardiac electrophysiology. Hundreds of thousands of people die from heart attack in the U.S. every year. Cardiac electrophysiology is important for understanding, diagnosing and treating electrical arrhythmias of the heart. Optical mapping is an increasingly popular tool for experimentally visualizing the electrical activity in the heart which can be seen in the picture. However, optical mapping is a computationally intensive procedure and presentday research is substantially hindered by the significant amount of time required to perform analysis even on the smallest amount of data. For example, 1 second of data requires 3.7 hours of computation. Through our research, we study the efficiency of different GPU implementations and our results show that GPU implementation of the optical mapping algorithm has a 33X speedup over the equivalent serial implementation. This will open new avenues of research that ultimately enable closed-loop feedback control of cardiac function that is not feasible using global measures of electrophysiology such as the electrocardiogram (ECG).

  • [BSD] High Content Optical Mapping for Cardiac Electrophysiology, Ali Irturk, Sam Wood, Alex Indaco, Ryan Kastner, International Workshop on Biomedical System Design (BSD 2010).
  • [BSD] Automation of Stem Cell derived Cardiomyocyte Selection and Analysis, Ali Irturk, Ryan Kastner, International Workshop on Biomedical System Design (BSD 2010).

4) Hardware System Design for Real-Time, Biplanar-Interferometric, Georeferenced Solutions from Simrad EK60 and ME70 Echosounder Data: The Simrad EK60 multi-frequency and ME70 multi-beam echosounders were designed for quantitative fisheries research and are standard equipment on all of the new NOAA Fisheries Survey Vessels (FSVs). The data from both of these systems can be processed using the multi-frequency biplanar interferometric (MBI) technique to achieve spatial resolutions for pelagic targets or bathymetry which are two to three orders of magnitude greater than with standard data processing. The MBI solutions can be used for improved imaging and quantitative evaluations of water column scatterers and their seabed habitats as shown in the picture. For example, bathymetry can be mapped with high subbeam resolution, and seabed echoes can be normalized by incidence angles, classified by roughness and hardness.

However, the data processing required to execute this algorithm is computationally intensive and therefore slow. Currently, processing is done using custom Matlab scripts and can take approximately 15 to 60 seconds per ME70 transmission for data collected to 250 to 2000-m ranges. We analyzed the algorithm, identified processing bottlenecks and are currently implementing the algorithm using a graphic processing unit (GPU). Depending on the quality of results and performance on the GPU, we may consider a field programmable gate array (FPGA) implementation. In either case, the hardware will interface with either the EK60, ME70, or both, and calculate MBI solutions in real-time. This system will provide the MBI results during data acquisition to enable real-time inspection of seabed and water column targets, and enhance decisions concerning adaptive survey operations and gear deployment, such as ROV navigation and trawl placement. This project is funded by NOAA.