This group is advancing the state-of-the-art in processor architecture and compilers, examining techniques that both expose higher levels of instruction-level parallelism (ILP) to the processor and allow the processor to exploit more of that parallelism. The current focus is on new architectural techniques and compiler optimizations aimed at high-performance processors and compiling for current and future high-ILP processors. Active areas of research include Simultaneous Multithreading (SMT), multi-core architectures and compiler optimizations for ILP.

The interaction between compilers and computer architecture is an important part of performance for future processors. This interaction is the basis for much of our compiler research. The topics being investigated include improving memory system performance through code and data layout compiler transformations, predicated execution, compiling for SMT, statically and dynamically estimating future behavior of an application, profiler-based optimizations, link-time and run-time optimizations, just-in-time compiling, and dynamic compilation.


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  • Publications of Brad Calder
  • Publications of Dean Tullsen