FINAL PROGRAM

Thursday, November 13, 1997

• 6:00 pm - 7:30 pm Workshop Registration
• 7:30 pm - 10.00 pm Reception and Dinner

Friday, November 14, 1997

• 8:00-8:15 Welcoming Remarks

Prab Varma, General Chair
Sujit Dey, Program Chair
• 8:15-9:30 SESSION 1 Addressing State Space Explosion in Formal Verification

Chair: C. Pixley, Motorola
1. A Framework for Equivalence Checking of Multi-Phase FSMs

G. Hasteer, Univ. of Illinois
A. Mathur, Silicon Graphics
P. Banerjee, Northwestern University
2. Automatic State Reduction Techniques for Hardware Systems

Modeled Using Uninterpreted Functions and Infinite Memory
R. Hojati, HDAC Inc.
A. J. Isles and R. K. Brayton, U.C. Berkeley
3. Environment Modeling and the Safe Removal of Universal Finite State Machines

R. Raimi, Motorola
R. Hojati, U.C. Berkeley
K. Namjoshi, Univ. of Texas at Austin
• 9:45-11:00  SESSION 2 High Level Design Validation

Chair: H. Yasuura, Kyushu University
1. Multi-dimensional Rule Checking for High-level Design Verification

J. Gong, C-T. Chen, K. Kucukcakar, Motorola, Inc.
2. High-Level Design and Validation of ATM Switch

S. P. Rajan, M. Fujita, Fujitsu Laboratories of America
K. Yuan, Univ. of Arizona
L-C. Lee, Avant! Corp.
3. On Design Error Detection of Different Validation Approaches For PowerPC Microprocessor Arrays

L-C. Wang, M. S. Abadir, Motorola
J. Zeng, IBM
• 11:15-12:30  SESSION 3  High Level Test Synthesis

Chair: S. Kadkade, Silicon Forest Research
1. Introducing Redundancy in RTL Data Paths to Reduce BIST Resources

I. Parulkar, S. K. Gupta, and M. A. Breuer,University of Southern California
2. Behavioral Test Set Matching for Effective BIST Through Synthesis of Test Behavior

I. G. Harris, Univ. of Massachusetts, Amherst
A. Orailoglu, Univ. of California - San Diego
3. High Level Synthesis for Partial Scan

M.L. Flottes, R. Pires, B. Rouzeyre, L. Volpe, LIRMM, France
• 12:30-1:45 Lunch
• 1:45-3:00 SESSION 4 Generating Manufacturing and Functional Tests

Chair: J. Abraham, Univ. of Texas at Austin
1. Method for Generating Test Stimuli that is Random as well as Self-Testing

R. Raina, Motorola Inc. and R. Molyneaux, IBM Corp.
2. Synthesis of Testable DSP-based Systems

C. Aktouf, G. Al-Hayek, and C. Robach, LCIS-ESISAR, France
3. Testcase Development for Large Telecom Systems

A. Jantsch, KTH-Electrum
J. Notbauer, T. Albrecht, Siemens AG Austria
• 3:15-4:00 SESSION 5 High Level Descriptions in Validation and Test

Chair: D. Ku, Escalade
1. Rectangle Covering for Optimal Evaluation of RTL Verilog in Compiled-Code Event-Driven Simulation

M. Jain, T-C. Lee, B. Agarwala, P. Deshmukh, Y-C. Hsu, Avant! Corp.
2. Enhanced Test Through Improved RTL Code Coverage

A. Miczo, Cypress Semiconductor
3. VHDL 200x - Requirements from Testbench-View

M. Bauer, W. Ecker, M. Heuchling -  Siemens AG
• 4:15-5:00 SESSION 6 Modeling and Testing Hardware/Software Systems

Chair: M. Fujita, Fujitsu Labs. of America
1. Modeling Reactive Systems in Java

R. Passerone, A. Sangiovanni Vincentelli, U.C. Berkeley
L. Lavagno, C. Passerone, C. Sansoe, Politecnico di Torino
2. Co-testing During Incremental Development of VLSI Component Test System

D. Kumamoto and T. Crossley, Schlumberger Austin Product Center
3. A Fault Injector System for a Microprocessor-Based Commerical Board

A. Benso, P. Prinetto, M. Rebaudengo, M.S. Reorda, Politecnico di Torino
• 6:30-8:00 Dinner
• 8:00-9:30 SESSION 7 Panel: Verification and Test: What have they got to do with each other?

Moderator: Y. Zorian, LogicVision
Panelists:
• M. Abadir, Motorola
• J. Abraham, Univ. of Texas at Austin
• T. Cheng, Univ. of California - Santa Barbara
• J-P. Masbou, Intel

Saturday, November 15, 1997

•  8:00-9:15  SESSION 8 Validating Hardware/Software Systems

Chair: B. Lin, Univ. of California - San Diego
1. An Interactive Validation Methodology for Embedded Systems

A. Dasdan, Univ. of Illinois at Urbana-Champaign
R. K. Gupta, Univ. of CA - Irvine
D. Ramanathan, Synopsys, Inc.
2. Facilities for Testing Control Software

P. J. Schoenmakers, Eindhoven University of Technology
3. A Software Approach for Fault Tolerance Improvement

A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda
Politecnico di Torino
• 9:30-10:45 SESSION 9 Hardware-Software Co-Simulation

Chair: R. Gupta, University of California, Irvine
1. VCI:  A VHDL-C Interface Generation Tool for Cosimulation

C.A. Valderrama and A. A. Jerraya TIMA/INPG
2. Fast Hardware-software Co-simulation Using Software Synthesis and Estimation

B. Tabbara, U.C. Berkeley,
L. Lavagno, Politecnico di Torino,
A. Sangiovanni-Vincentelli, U.C. Berkeley
3. Synchronization Overhead Reduction in Timed Cosimulation

S. Yoo and K. Choi, Seoul National University
• 11:00-12:15 SESSION 10 Verification and Test of System-on-a-Chip

Chair: Y. Zorian, LogicVision
1. Debugging of Systems on a Chip:  Embedded Triggers

G. Jan van Rootselaar, F. Bouwman, E. Jan Mariniseen, M. Verstraelen
Philips Research Labs.
2. Output Response Compaction in Core-Based Designs

B. Pouya and N. A. Touba, University of Texas at Austin
3. High Level Testability of Embedded Cores

B. Greene and J. El-Ziq, Synopsys, Inc.
• 12:15-1:30 Lunch
• 1:30-2:45  SESSION 11 Verification of Processors

Chair: R. Roy, Intel
1. Specification and Verification of the ARM2 Microprocessor

J.K. Huggins, GMI Engineering and Management Inst.
D. Van Campenhout, University of Michigan
2. High-Level Design Verification of Microprocessors via Error Modeling

H. Al-Asaad, D. Van Campenhout, J. P. Hayes, T. Mudge, and R. Brown, University of Michigan
3. Superscalar Processor Validation at the Microarchitecture Level

N. Utamaphethai, R.D. (Shawn) Blanton, and J. P. Shen, Carnegie Mellon University
• 3:00-4:15 SESSION 12:  Verification of Embedded Systems: Where are we? Where do we need to go?

Moderator: V. Nagasamy, VSIS
Panelists:
• J. Kumar, Motorola
• S. Leef, Mentor Graphics
• G. Martin, Cadence Design Systems (Alta)
• S. Soman, LSI Logic
• P. Marwedel, Univ. of Dortmund
• H. Date, ISIT