I. Introduction
II. Instruction Set Architecture
III. Performance
IV. Computer Arithmetic, part 2
V. Single-cycle CPU (datapath and control), multicycle CPU, microprogramming and exceptions.
VI. Pipelining, data hazards, control hazards, advanced pipelining.
VII. Memory -- Caches, more caches, and virtual memory.
VIII. Multiprocessors.

If you have comments or suggestions, email me at tullsen@cs.ucsd.edu