Lab Assignment #4

Lab Assignment #4, Due February 26, 1999

Due 5:00PM, to be placed under the door of AP&M'4840

Introduction: This lab consists of two parts: (i) Implementation of two adders: ripple-carry adder and carry look-ahead adder on LogicWorks, (ii) Implementation of hazard-free circuits. The second part consists of two subsections: converting a design with hazards to a hazard free design and verification of the final design on LogicWorks via simulation and on breadboard using discrete logic gates.

General Information

In this experiment the delays associated with the logic gates to be used during the simulation play an important role. In the previous experiments you were using the default delay values supplied by LogicWorks. However, in this experiment we want to modify these delays to include the timings of the discrete components. Before starting this experiment please read the "Schematic Simulator Menu Commands: Delay Box" section from LogicWorks^TM3 Interactive Circuit Design Software For Windows and Macintosh. For each component you are going to use, set the delays according to the following table.

Name	Gate Delay(ns)	Name	Gate Delay(ns)
Inverter	1
AND	2.4	n-input AND	1.6 + n * 0.4
OR	2.4	n-input OR	1.6 + n * 0.4
NAND	1.4	n-input NAND	0.6 + n * 0.4
NOR	1.4	n-input NOR	0.6 + n * 0.4
XOR	4.2
XNOR	3.2

Please read the section "Device Editor" from LogicWorks^TM3 Interactive Circuit Design Software For Windows and Macintosh. You will need to use this information in this lab.

Part 1: Adder Implementations

The object of this part of the exercise is to familiarize yourself with different implementations of adders. In this part of the exercise, you will implement a ripple-carry adder and a look-ahead-carry adder. In both implementations you will do a standard (using AND/OR) and the associated NAND/NAND implementation. In all subcircuits set the delays of the gates according to the table given in the previous General Information section.

Implement both a Half-Adder and a Full-Adder using the standard implementations from your book (using XOR/AND/OR gates) and NAND/NAND implementation. Create a subcircuit for each of these implementations. Name the implementation according to the following naming convention:

Half-Adder (standard): HA_S
Full-Adder (standard): FA_S
Half-Adder (NAND-NAND): HA_N
Full-Adder (NAND-NAND): FA_N

Using the previously designed full adders, implement a 6-bit ripple-carry adder (one with FA_S and one with FA_N). Measure the delay of this adder for various input combinations. The delay of an adder is the time difference between the time you change the input and the time when the output does not change any more. Please include the addition of (111111 to 000001) in your delay measurements. Please also include a printout of the timing of the simulations in your report. Try to get the worst case delay (or critical path delay).

Implement a carry-look-ahead adder. Follow these steps in your implementation.

Create a subcircuit with 2 6-bit inputs to generate "generate" and "propagate" terms for the carry-look-ahead adder.

Implement a carry-look-ahead generator circuit. The inputs to this circuit should be g₀...g₅, p₀...p₅ and c₀. The output of this circuit should be c₁...c₆ & g_(0,5), p_(0,5).

Combining the building blocks, create a 6-bit carry-look-ahead adder. The inputs to this circuit should be x₀...x₅, y₀...y₅ and c₀, and the outputs should be s₀...s₅ and g_(0,5), p_(0,5).

For the above implementation use both standard and NAND-NAND implementation. In effect, you will have two sets of all of the aforementioned circuits. Use _S and _N as a naming convention. Measure the delay of your carry-look-ahead adder circuit using the method that you used for ripple-carry adder.

Now you are going to implement 3-different 12 bit adders. Choose the fastest implementations for this part. Implement the following 12-bit adders:

12-bit ripple-carry adder using 6-bit ripple carry adders
12-bit carry-look-ahead adder (single-level) using 6-bit look-ahead-carry adders
12-bit carry-look-ahead adder (two- level) using 6-bit look-ahead-carry adders

Please measure the critical path delays. In which implementation, do you get the best delay time?

Information about various adder implementations can be found in your text, Gajski, Principles of Digital Design, sections-5.1 & 5.2.

Part 2: Logic Functions

The object of this part of the exercise is to learn about the implementation of hazard-free circuits. In this part you are given the following function F(A,B,C,D) (as a K-map):

CD AB

1. Find the minimal sum-of-products implementation of F.
2. Identify the static hazards.
3. Find the hazard free implementation of this function in sum of products form.
4. Draw the schematic of the implementation with static-hazards on LogicWorks and set the delay of the components as given in the General Information section. Perform logic simulation to indicate all possible hazards in this circuit. Include a printout of this simulation in your report.
5. Draw the schematic of your own hazard-free implementation with the same delay settings. Perform logic simulation to verify that the previously seen static-hazards no longer exist. Information about static-hazards and implementation of hazard-free circuits can be found in your text, Gajski, Principles of Digital Design, section-4.7.

If you are certain that your design is hazard-free now, you can advance to the next step in this exercise. Implement the circuit with static hazards and the hazard-free version on the breadboard using discrete components from your Lab Kit. You can either use an AND-OR implementation or a NAND-NAND implementation in this part. The NAND-NAND implementation preserves the hazardous (or hazard-free) behavior.

The difficulty in this part is that there is no direct way of observing the hazards (glitches at the output). Therefore, you will use an indirect way to observe the possibly occurring glitches. In order to be able to do that, you will use an edge-triggered D flip-flop, which is a single bit memory element. When you apply a low-to-high pulse to the CLK input of the D flip-flop, the input to the flip-flop is transferred to and stored in the flip-flop. The stored value remains untouched as long as there is no low-to-high pulse at the CLK input. The D flip-flop in your lab kit also has CLR(clear) and PRE(preset) inputs. Since a circuit with a static-hazard creates a small pulse of level low for a few nanoseconds, this may serve as a low-to-high pulse to the CLK input of the flip-flop. Therefore, the method to observe the glitch is as follows:

Find the appropriate input values to stimulate the hazard in the implementation. Apply these input values to the circuit.
CLR the flip-flop using CLR input. Connect +5V to the D input and connect the output of your circuit to the CLK input.
Change the input to observe the hazard. If there is a hazard in this implementation, the output of the flip-flop would go to high. Otherwise it must stay at low.

Get a signature from your TA's for both the hazard-free and hazardous implementations of the function F. Provide the simulation results while you present your circuits.

Signature (hazardous circuit) _______________________________

Signature (hazard-free circuit) _______________________________

Requirements:
For the first part, return a printout of all your designs (including the printouts of the subcircuits you have created) together with the results that you are asked to return in the first part of this hand-out. For the second part, return the simulation results for both hazardous and hazard-free implementations. The results should include the schematics and the timing simulation results.