Announcements

1. In the CSE140l library you will find the following elements: 3COMP, 3CLOCK, and 3ALARM. These components will be of great help to you, when implementing the first lab assignement. While you can use the libraries of primitives gates and create your own components for accomplishing each assignment, we recommend that you use the components from the CSE140l library. These components can be hooked together to implement the correct design. A description of these components follows.

3COMP - tree bit comparator. The output is 1, when the two 3-bit inputs are equal, and 0 otherwise.
3ALARM - this component allows you to set the alarm time. The inputs A, AM(inutes), AH(our) can be used to set the alarm time.
3CLOCK - this is the clock component. It has simular inputs as the alarm component for seting the time. This is the component that implements the real time clock. The outputs of this component show the current time.

2. For the LogicWorks part of the assignements we want the design file (*.cct) to be turned in. In order to do this, you should use the turnin command. The usage of this command is very simple - the only thing you have to do is to type "turnin -c cs140w file_name". For more detailed information of how to use turnin, type "help instruct" and select topic 2.

3. Please send all your emails with technical questions to the Head TA (chebrolu@cs.ucsd.edu), not to the instructor.

4. For the LogicWorks part of the assignment, please turn in also a text file with following explanation: the group member names, what was the work separation, does the design work and if not what were the problems, and anything else you feel important. Please be SHORT.

Be careful when turning it in. You should tar both files (*.cct and readme.txt) and turnin the combined file. You can use the following command to do this steps at once: "tar cvf - yourdesignfilename.cct readme.txt | turnin -c cs140w". You can turnin only one file. If you use the turnin command twice, the first file will be replaced.

5. If you name two wires with same name, these wires will be connected. There might be no wire between them, but they are still connected. Be careful with this.

6. You can find the CSE140l library (CSE140l.CLF) in the public directory (~/../public) as well as the ExampleClock.cct sample design.

7. In order to copy your file from the Macs to the Solaris, you have to ftp it. You need to do this, because the turnin procedure runs on the ieng9.ucsd.edu machine. You have to be logged with you class accounts in ieng9. You can use the program Fetch, which is an ftp client for Mac. Of course, you can use any other ftp client (for example, you can upload the files with Netscape Comunicator).

8. For the second assignment (the Booth's multiplier) as the A/S control signal for the Adder, you have to use the least significand bit of the Multiplier (of course, as you can see from the general schematic given to you). The output Add/Sub from the control unit is dummy.

9. You can get a solution for the 2-nd lab assignment here. Your can also find this file at public directory (~/../public).

10. Due to the uneven student concentration in the initial office hours schedule, we have new schedule. Please look at the home page for the exact hours. Now, the Thursday evening hours have been increased (of the due weeks).

11. Please, download the new version of CSE140l library. You can find it on the class home page or in (~/../public). There was a glitch on a LoadI signal in the previous version and since you are using asynchronous load counter, this glitch causes erroneous behaviour. Of course, you could work around it (you could identify the glitch by simulation) by masking the signal with clock (anding both signal) before wiring to the counter, or use synchronious counters.

12. The late submission (with a penalty) for the 3-th lab assignment is Tuesday instead of Monday (because of the Monday vacation).