Time: TuTh 3:55-5:15, Place: AP&M 4218
Instructor: Dean Tullsen
Office Hours: by appt.
(Micro)
Eager Writeback - a Technique for Improving Bandwidth Utilization
H.-H. Lee, G. S. Tyson (University of Michigan), M. Farrens (University
of California, Davis)
Silent Stores for Free
K. M. Lepak, M. H. Lipasti (University of Wisconsin - Madison)
Predictor-Directed Stream Buffers
T. Sherwood, S. Sair, B. Calder (University of California, San Diego)
On Pipelining Dynamic Instruction Scheduling Logic
J. Stark (Intel), M. D. Brown, Y. N. Patt (University of Texas at Austin)
The Impact of Delay on the Design of Branch Predictors
D. A. Jimenez, S. W. Keckler, C. Lin (University of Texas at Austin)
?Two-level Hierarchical Register File Organization for VLIW Processors
J. Zalamea, J. Llosa, E. Ayguade, M. Valero (Universitat Politecnica
de Catalunya)
PipeRench Implementation of the Instruction Path Coprocessor
Y. Chou, P. Pillai, H. Schmit, J. P. Shen (Carnegie Mellon University)
Very Low Power Pipelines using Significance Compression
R. Canal, A. Gonzalez, J. E. Smith (University of Wisconsin - Madison)
A Static Power Model for Architects
J. A. Butts, G. Sohi (University of Wisconsin - Madison)
A Framework for Dynamic Energy-Efficiency and Temperature Management
W. Huang, J. Renau, S.-M. Yoo, J. Torrellas (University of Illinois
at Urbana-Champaign)
Register Integration: A Simple and Efficient Implementation of Squash
Re-Use
A. Roth, G. S. Sohi (University of Wisconsin - Madison)
Memory Hierarchy Reconfiguration For Energy And Performance In General-Purpose
Processor Architectures
R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, S. Dwarkadas (University
of Rochester)
Frequent Value Compression in Data Caches
J. Yang, Y. Zhang, R. Gupta (University of Arizona)
Relational Profiling: Enabling Thread Level Parallelism in Virtual Machines
T. H. Heil, J. E. Smith (University of Wisconsin - Madison)
Instruction Distribution Heuristics for Quad-Clustered, Dynamically-Scheduled,
Superscalar Processors
A. Baniasadi (Northwestern University), A. Moshovos (University of
Toronto)
Performance Improvement with Circuit-Level Speculation
T. Liu, S.-L. Lu (Intel)
(HPCA)
"Data-flow Prescheduling for Large Instruction Windows in Out-of-Order
Processors"
Pierre Michaud and André Seznec, IRISA/INRIA
"Speculative Data-Driven Multithreading"
Amir Roth and Gurindar Sohi, University of Wisconsin at Madison
"Performance of Hardware Compressed Main Memory"
Bulent Abali, Hubertus Franke, Xiaowei Shen, Dan E. Poff, and
T. Basil Smith, IBM T.J. Watson Research Center
"DRAM Energy Management Using Software and Hardware Directed
Power Mode Control"
Victor Delaluz, Mahmut Kandemir, Vijaykrishnan N., Anand Sivasubramaniam,
and Mary Jane Irwin, Penn State University
"Dynamic Thermal Management for High-Performance Microprocessors"
David Brooks and Margaret Martonosi, Princeton University
"Dynamic Prediction of the Critical Performance Path"
Eric Tune, Dongning Liang, Dean Tullsen, and Brad Calder, UCSD
"Dynamic Branch Prediction with Perceptrons"
Daniel Jimenez and Calvin Lin, University of Texas at Austin
"Branch History Guided Instruction Prefetching"
Viji Srinivasan, Edward Davidson, Gary Tyson, Mark Charney,
and Thomas Puzak, University of Michigan and IBM T.J. Watson Research Center
"Reducing DRAM Latencies with an Integrated Memory Hierarchy
Design"
Wei-fen Lin, Steven Reinhardt, and Doug Burger Universities
of Michigan and Texas at Austin
ASPLOS
Designing Computer Systems with MEMS-based Storage
David Nagle, Steven Schlosser, John Linwood Griffin, Gregory Ganger
(Carnegie Mellon University)
Efficient and Flexible Value Sampling
Michael Burrows (Compaq SRC), Ulfar Erlingson (deCODE Genetics), Shun-Tak
Leung (Compaq SRC), Mark Vandevoorde (AltaVista), Carl Waldspurger (VMWare),
Kip Walker (CMU), Bill Weihl (Akamai)
Software Profiling for Hot Path Prediction: Less is More
Evelyn Duesterwald, Vasanth Bala (Hewlett Packard Labs)
OS and Compiler Considerations in the Design of the IA-64 Architecture
Rumi Zahir (Intel Corporation), Jonathan Ross (Hewlett Packard Company),
Dale Morris (Hewlett Packard Company), Drew Hess (Lucas Digital Ltd.)
Hardware Support for Dynamic Management of Compiler-Directed Computation
Reuse
Daniel Connors, Hillery Hunter, Ben-Chung Cheng, Wen-Mei Hwu (UIUC)
Symbiotic Jobscheduling for a Simultaneous Multithreading Processor
Allan Snavely, Dean Tullsen (University of California, San Diego)
An Analysis of Operating System Behavior on a Simultaneous Multithreaded
Architecture
Joshua Redstone, Hank Levy, Susan Eggers (University of Washington)