CSE 141 Homework Assignments

Winter 1998, Instructor: Dean Tullsen

Homework Assignments:

• HW #1: Due Thursday, January 15
• 3.1, 3.6, 3.9, 3.10, 3.14, 3.19
• HW #2: Due Tuesday, January 27
• 2.3, 2.4, 2.9 (ignore cost-effective part), 2.11, 2.12, 2.41, 2.42, 3.15, 3.17, 4.2, 4.9, 4.10, 4.14, 4.18
• HW #3: Due Thursday, February 5
• 4.28, 4.31, 4.46, 4.55, 5.5, 5.8, 5.9, 5.10, 5.15
• HW #4: Due Thursday, February 12
• 5.16, 5.23, 5.24, 6.2, 6.4, 6.9, 6.11
• HW #5: Due Tuesday, February 24
• 6.14, 6.15, 6.19, 6.28, 6.29, 6.30
• web-surfing assignment: How many pipeline stages do the following processors have? The Intel Pentium, Pentium Pro, DEC Alpha 21264, MIPS R10000, PowerPC 620.
• HW #6: Due Thursday, March 5
• 7.8 (note the word, not byte, addresses), 7.9, 7.15, 7.16, 7.17, 7.18, 7.20, 7.23
• web-surf 2: Give me the superscalar width (how many instructions per cycle can they fetch and/or execute per cycle) for the following processors: Alpha 21164, 21264, Pentium, Pentium Pro, MIPS R10000. Are they in-order or out-of-order processors?
• HW #7: Due Thursday, March 12
• 7.32, 7.33, 7.35, 7.45
• web-surf 3: What are the on-chip cache sizes and associativity for the following processors: Pentium, Pentium Pro, Alpha 21164, 21264?

If you have comments or suggestions, email me at tullsen@cs.ucsd.edu