How to Use the Unix 'make' Facility
		 -----------------------------------

The Unix make facility is a program for maintaining computer programs.
Make provides a simple mechanism for maintaining up-to-date versions
of programs that result from many operations on a number of files.  It
is possible to tell make the sequence of commands that create certain
files, and the list of files that require other files to be current
before the operations can be done.  Whenever a change is made in any
part of the program, the make command will create the proper files
simply, correctly, and with a minimum amount of effort.

The basic operation of make is to update a target file by ensuring
that all of the files on which it depends exist and are up to date,
then creating the target if it has not been modified since its
dependents were.  Technically speaking, make does a depth-first search
of the graph of dependencies.

Consider the following simple example. This is for a class 
called MyClass and the program is a test program for that class,
but could be any application program that uses the class. 

	test_myclass.cxx
		contains the main body of the program to test your
                implementation of the class MyClass. 
		(This is the "application file".)

	myclass.h
 		Is the header file that contains the definition of 
		the class MyClass.

	myclass.cxx	
		contains the definitions of the member functions and
		overloaded operators for the class MyClass.
		(This is the "implementation file".)


When you type 'make', the program will look, by default, for a file
named "makefile" (this is called the makefile).  The format of this file
is a list of entries (called target entries) of the following form

target: dependencies
	command_1
	command_2
	command_n

The target is the thing you want to "make", the dependencies are the
things upon which the making action depends, and the commands are the
instructions to the operating system telling it how to create the
target.  COMMAND LINES MUST START WITH A TAB.

Going back to the example above, a makefile which tells make to "do
the right thing" given the usual dependencies would have the 
following entries:


tester: test_myclass.o myclass.o 
	CC test_myclass.o myclass.o -o tester

test_myclass.o: test_myclass.cxx  myclass.h
	CC -c test_myclass.cxx

myclass.o: myclass.cxx myclass.h
	CC -c myclass.cxx


What this makefile says is that the executable program "tester" is
dependent on the existence of the object files test_myclass.o and
myclass.o, and, given those object files, the command appearing in the
second line is how the target ("tester") is generated from the object
files. The command CC in this case links the files test_myclass.o and
myclass.o and puts the resulting executable code in the file tester.
The same is true later in the file for the object files as
targets.  Note that the -o option to CC (in fact, most compilers)
tells the compiler to produce an output file (executable) of the
specified name OTHER THAN the default "a.out" (unless, of course you
were to specify "a.out" as the name following the -o option).  The -c
option tells the compiler to produce only an object file (not an
executable), which can be used later on for linking with other object
files.

The make facility is actually much more powerful than this simple
explanation would lead you to believe, though the description provided
above should be sufficient for what is required in this course.  The
curious reader is directly to any bookstore trading in computer
material where he/she will find entire texts devoted to the use of
make.