Welcome to CSE 148. In this class, you will design an advanced general-purpose processor that executes the MIPS ISA. Your goal is to create a processor that executes a few target benchmarks as quickly as possible. Everyone will start with the same baseline design (which executes the MIPS ISA correctly) written in system verilog. Each group (typically 2 people) will add a few advanced optimizations, such as the following: superscalar, out-of-order execution, advanced cache optimizations, advanced branch predictors, register renaming, multithreading, etc.

This is an extremely demanding class, intended for students seeking the type of challenge they rarely get from a single class in a quarter system. Doing well in this class typically involves making significant sacrifices in your other classes. Making a half-hearted attempt at this class (ie, treating it like any other class) usually goes very badly.

Students should be very confident in their verilog design skills and in their grasp of basic pipelined computer architecture. We run full speed from day one -- there is no chance to catch up if you aren't ready to go from the beginning.

We will get most of our information from the primary sources -- research papers in the literature. Students will be expected to be able to read these papers and in some cases present these papers.

The info you need for this class will be found on Canvas. Please go there frequently to keep up with the class.

This is important. Because we start quickly and form groups quickly, no one who is not in attendance for BOTH of the first two classes will be allowed to remain in the course