BANG
E5345 ("Clovertown"), Intel Core Architecture
Clock speed: 2.33GHz
2 dual-core procesors in a socket
2 sockets per node
Write Update policy: writeback

Data Caches: 64 byte line size
L1: 32KB,   8way, 1 per core, 3 cycle access latency
L2: 2x4MB, 16way, 2 cores share an L2 (Unified), ~14 cycle access latency

DTLB
DTLB0 for 4-KByte pages: 16 entries (loads only)
DTLB1 for 4-KByte pages: 256 entries (stores, loads that missed in DTLB0)
DTLB0 miss: 2 cycles
DTLB1 hit: 2 cycles

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General Guidelines
Write Combining
Write combining (WC) improves performance in two ways:
* On a write miss to the first-level cache, it allows multiple stores to the same cache line to occur before that cache line is read for ownership (RFO) from further out in the cache/memory hierarchy. Then the rest of line is read, and the bytes that have not been written are combined with the unmodified bytes in the returned line.

* Write combining allows multiple writes to be assembled and written further out in the cache hierarchy as a unit. This saves port and bus traffic. Saving traffic is particularly important for avoiding partial writes to uncached memory.


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Sources:
/sys/devices/system/cpu
/proc/cpuinfo

Intel 64 and IA-32 Architectures Optimization Reference Manual
http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html
Tables 2-16 (Intel Core) an 2-20 (Intel core i7)

http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html

Samuel Williams, Jonathan Carter, Leonid Oliker, John Shalf, and Katherine Yelick. 2009. Optimization of a lattice Boltzmann computation on state-of-the-art multicore platforms. J. Parallel Distrib. Comput. 69, 9 (September 2009), 762-777. http://dx.doi.org/10.1016/j.jpdc.2009.04.002
http://crd.lbl.gov/assets/pubs_presos/jpdc09-lbmhd.pdf