Course Description

From this course, you will learn correct hardware design practices suitable for processor design. You will design, implement and test your own processor, and learn about computer architecture in the best way -- by doing.

This course is taught in tandem with CSE 141. Unless you have discussed it with me, you should be enrolled in both.

Guidelines and Grading Info.

• REQUIRED: PIAZZA
• I will be using PIAZZA for the majority of class correspondence. Piazza is great. It connects everyone in the class as well as the instructors. Use it to ask questions, discuss the labs, etc. Myself and the TAs will be checking Piazza regularly to chime in.
• URL: https://piazza.com/ucsd/winter2013/cse141l/home
• The initial class roster will receive invites, however it is your responsibility to make sure you are signed up. If you are not already on, click the link and sign up.
• I will put labs and other materials on Piazza from time to time in PDF format.

• Assignments
• There will be 4 lab assignments. Each will require a written report. There will be no midterms or finals associated with this class. The final grade will be determined by the quality of the lab reports and the completeness and quality of the lab work (as demonstrated in the reports).
• Some but not all of the labs will require the Xilinx tools, which everyone should be familiar with. If you are not, you must take some time the first two weeks to familiarize yourself with it. After that, it will be too late -- you need to be ready to run at that point.
• Most (but not all) of the labs can be done in groups of 1 to 3. Lab reports are to be done collaboratively with your fellow group members, except when specifically instructed otherwise.  Changing, splitting, merging of groups is only to be done with the permission of the instructor, and such permission is typically not given.
• Labs will typically be due two weeks after they are assigned.

• Grading
• The grade for 141L will be based primarily on 4 lab reports. I expect that most students will complete the lab assignments as specified; thus, the quality of the lab reports will likely be the most important factor in determining grades.  Attendance will also be factored into grades (in a major way) somehow.
• Late assignments are not encouraged. All lab reports are due at the beginning of class on Tuesday.  Anything else is considered late.  You will have one grace weekend during the quarter. I.e., you can turn one assignment in late, as long as it is in my office (under the door) before 9 a.m. on Monday. I recommend not spending that grace time frivolously early in the quarter. After you have spent your grace days, late assignments will be accepted, but with significant penalties. We will make every effort to return assignments to you in a timely manner -- limiting your ability to turn things in late is, unfortunately, critical to that goal.
• All 4 lab reports are required.  You must do a credible job on each to pass the class.

• Integrity
• Cheating WILL be taken seriously. It is not fair to honest students to take cheating lightly, nor is it fair to the cheater to let him/her go on thinking that is a reasonable alternative in life. Don't test me on this one.
• The following is not considered cheating:
  • discussing the tools or logic design techniques with other groups.
• The following is:
  -Copying lab designs from someone who is not your partner, or lab report text from anyone.
  -Viewing lab designs or lab reports from anyone who is not your partner, including those who have taken the class in previous years.
  -Altering timing data produced by Xilinx, e.g. to make a non-working design appear to be working.
• Penalties -- anyone copying information or having information copied on a lab, or any other violation of class policy, will receive an F in the class and will not be allowed to drop.  They will be reported to their college dean.  If you can prove non-cooperative copying took place, your grade may be restored, but you must prove it to the dean -- I don't want to be involved.

Xilinx and Verilog Resources

Xilinx Schematics tutorial from cse140L Summer 2007
http://www.cse.ucsd.edu/classes/su07/cse140L/140L_tutorial_1_-_summer_2007.pdf
http://www.cse.ucsd.edu/classes/su07/cse140L/140L_tutorial_2_-_summer_2007.pdf

Xilinx Verliog/VHDL tutorial from cse140L Summer 2007
http://www.cse.ucsd.edu/classes/su07/cse140L/140L_tutorial_3_-_summer_2007.pdf

Verilog Overview/tutorial by Sat Garcia
http://www.cse.ucsd.edu/classes/sp07/cse141/slides/vlog-tutorial.pdf
http://www.cse.ucsd.edu/classes/sp07/cse141/slides/verilog_deux.pdf

Verilog Fundamentals by Krste Asanovic at MIT
http://csg.csail.mit.edu/6.375/handouts/lectures/L02-Verilog-Fundamentals.pdf

Verilog Design Examples by Krste Asanovic at MIT (synthesis friendly)
http://csg.csail.mit.edu/6.375/handouts/lectures/L03-Verilog-Design-Examples-1.pdf

At some point, we will attempt to synthesize our circuits (e.g., to extract timing). These resources were selected because they should all be synthesis friendly. Many tutorials and verilog code available on the internet are not.

Lab Resources

• Xilinx Foundation tools are available in CSE B240 and CSE B250. Not sure what version or how up to date. If you go and find out, please let me know.