cse141: Introduction to Computer Architecture

CENTER HALL 214 (Starting from Jan 3rd)
Lectures Tue. & Thu., 5:00p-6:20p (Center Hall 214) ; Disc. section Mon. 5:00p-5:50p (Cognitive Science Building 001)
Winter, 2011
Shortcuts: Schedule Homeworks Projects

Instructor

Steven Swanson

Email:

swanson

cs.ucsd.edu

IM (not email): professorswanson@{AIM, Yahoo!, google talk, MS Messenger}
Office: EBU3B 3212
Office Hours: Tues. 6:30-7:30 (EBU3 B230); Thur. 10:30-11:30 (ebu3b 3212); or by appointment
UCSD homepage

Teaching Assistants

Sanath Kumar

Email:

skramesh

cs.ucsd.edu

IM (not email): skramesh [at] eng.ucsd.edu
Office: B260A
Office Hours: Tuesday, Thursday: 11.00a - 12.00p, or by appointment

Bharathan Balaji

Email:

bbalaji

ucsd.edu

IM (not email): get.bharathan@gmail
Office: B260A
Office Hours: Monday: 2.00p - 3.00p, Wednesday: 4.00p - 5.00p, or by appointment

Vineet Kumar

Email:

vkumar

cs.ucsd.edu

IM (not email): vkumar@eng.ucsd.edu
Office: B240A
Office Hours: Monday, Wednesday: 10.00a-11.00a, or by appointment

Course discussion board: cse141. Required reading. Get signed up.

Course Description

This course will describe the basics of modern processor operation. Topics include computer system performance, instruction set architectures, pipelining, branch prediction, memory-hierarchy design, and a brief introduction to multiprocessor architecture issues.

This course is taught in tandem with 141L. Unless you have discussed it with you me, you should be in enrolled in both.

Text books

Required: Patterson & Hennessy, Computer Organization and Design: The Hardware/Software Interface, Patterson & Hennessy, Morgan Kaufmann, 4th Edition
Required: Other assigned readings throughout the quarter.
Optional: The History of Computing This a great set of lectures from a course taught at UCSD/UW/Berkeley three years ago. Most of them are buy the folks that actually made the history (Steve Wozniak, Ray Ozzie, Gordon Bell, etc.).

Grading

In addition to the contributions below, class participation (speaking up in class, attending office hours, etc.) can raise your grade up to one "notch" (e.g., B to B+).

Homework	10%	Homeworks will be assigned through the course. They are due on Thursdays.
Quizzes	10%	Every Thursday there will be a quiz.
Project	15%	Design your own ISA! See below
Midterm	25%	Self explanatory.
Final	35%	The final will be cummulative.
Class participation	5%	Speak up in class. Contribute to the web board. Come to office hours.

Additional notes about grades in this course:

Calculating grades I compute grades using an Excel spread sheet. In the interests of transparancy, the current grade sheet (with identifying information removed) is avaiable in either XLS format. The grade sheet contains all the information about curves and how the grades are computed. It is somewhat sophisticated, if you find bugs please bring them to my attention. Please note that some versions of OpenOffice do not perform the calculations properly, and will give incorrect results.

The grading systems is based on a 13 point (F through A+) scale. For each assignment/test/etc, the sheet computes the letter grade (rounding up, when needed) according to a curve for each assignment (specified at the bottom of each assignments column). Your final grade is the weighted average of these grades.

We do our best to record grades accurately, but you should double-check.
Errors in grading If you feel there has been an error in how an assignment or test was graded, you have one week from when the assignment is return to bring it to our attention. You must submit (via email to the instructor and the appropriate TAs) a written description of the problem.

For arithmetic errors (adding up points etc.) you do not need to submit anything in writing, but the one week limit still applies.
Final grades If you have a problem with your final grade in the course, send me email and we can set up an appoinment to discuss it. Like you, I generally go on a vacation after the quarter ends, so it may take a little while for me to get back to you and the meeting will likely be the next quarter. If the problem needs to be resolved sooner make that clear in your email (like in the first line).

Schedule

I will post the slides for most lectures. Since the slides contain material I am not allowed to distribute publically, they are password protected. I have posted the username and password to the web board.

Reading should be done before class on the day they are listed. It is essential that you do the readings. I will not cover everything you are responsible for in class.

Date	Topic	Readings	Slides	Due	Notes
Tuesday, January 4	Introduction and Administrivia		00_Introduction.pdf
Thursday, January 6	Instruction Set Design	Read: 1.1-1.3; 2.1-2.7; Key points: Types of machines and general terminology. Parts of the machine. Key components of an instruction set. Operand storage in registers and memory. Arithmetic, logical, and memory operations in MIPS	01_ISA.pdf
Tuesday, January 11	Instruction Set Design	Read: 2.8, 2.10, 2.12-2.13, 2.16-2.19 Skim/Review: 2.4, 2.6, 2.9, 2.14; Key points: Function calls, translation from source code to machine code, the diversity of ISA design decisions between MIPS, ARM, and x86.	03_ISA.pdf, 04_Project.pdf	Assignment 1-1; Assignment 1-2;
Thursday, January 13	Instruction Set Design	Read: 2.8, 2.10, 2.12-2.13, 2.16-2.19 Skim/Review: 2.4, 2.6, 2.9, 2.14; Key points: Function calls, translation from source code to machine code, the diversity of ISA design decisions between MIPS and x86.	S_x86_64.pdf, 05_ISA.pdf, ../x86, ToolsOverview.pdf
Tuesday, January 18	Measuring Performance	Read: 1.4-1.9; Key points: Speedup. The performance equation. Amdahl's law. Benchmarks and their short comings	06_performance.pdf, Q01_key.pdf
Thursday, January 20	Measuring performance	Read: 1.4-1.9; Key points: Speedup. The performance equation. Amdahl's law. Benchmarks and their short comings	07_performance.pdf, MP0_ISA.pdf, S_MemAndSRAM.pdf	Assignment 2;
Tuesday, January 25	Performance/Single Cycle processors	Read: 4.1-4.4; Key points: Designing a single-cycle datapath, datapath vs. control, clocking, control signals, decoding, handling branches. Review Appendix C if your logic design is rusty.	08_SingleCycleProcessor.pdf, 09_CodeAnalysisExample-opt.xls, x86Instructions.pdf, Q02_key.pdf, Q03_key.pdf
Thursday, January 27	Single Cycle to Pipelining	Read: 4.1-4.4; Key points: Designing a single-cycle datapath, datapath vs. control, clocking, control signals, decoding, handling branches. Review Appendix C if your logic design is rusty.	08-5_SingleCycleProcessor.pdf, S_DRAM.pdf, S_ProjectAlgorithm.pdf
Tuesday, February 1	Data hazards; SRAM	Read: 4.5-4.6; Key points: Basic of pipelining. Pipelined datapath layout. Pipeline registers. Limitations of pipelining. Data hazards.	10_Pipelining.pdf, 11_Hazards.pdf, Q04_key.pdf
Thursday, February 3	Control hazards; DRAM	Read: 4.7-4.9	12_Branches.pdf, MP2_WhereAmI.pdf	Assignment 3-1; Assignment 3-2;
Tuesday, February 8	Branch Prediction, Introduction to Caching	Read: 4.10-4.14, except 4.12	13_Branches.pdf, 14_Caches_intro.pdf, Midterm.pdf, Q05_key.pdf	Project 1;
Thursday, February 10	Miterm review		Q06_key.pdf	Assignment 4;
Tuesday, February 15	Midterm	TBA
Thursday, February 17	Guest Speaker: Dr. Michael Taylor. Cache eviction policies.	TBA	15_Caches_detail.pdf	Assignment 5;
Tuesday, February 22	Memory Systems	Read: 5.1-5.3. Key points: Cache interference and associativity. Direct-mapped and fully-associative caches. The three C's of cache misses.	16_Cache_advanced.pdf, 17_Caches_detail.pdf
Thursday, February 24	Advanced caching and VM	Read: 5.4-5.5	18_MidtermGrades.pdf, 19_VirtualMemory.key.pdf, 20_x86Memory.pdf	Assignment 6;
Tuesday, March 1	Virtual Memory	TBA	21_VirtualMemory.pdf, 22_IO.pdf
Thursday, March 3	I/O	6.1-6.13	23_IO.pdf	Assignment 7;
Tuesday, March 8	Multiprocessors/Advanced Pipelining	7.1-7.3; 7.7	Q08_key.pdf, Q09_key.pdf, 26_CMPs.pdf, 24_Moneta.pdf, 25_SuperScalarSMT.pdf
Thursday, March 10	CMPs/Wrap up and Final review	TBA	Q10_key.pdf, 26_CMPs.pdf, 2011WinterCSE141Midterm-key.pdf	Assignment 8; Assignment 9;
Thursday, March 17	Final Exam				7.00p-9.59p

Integrity Policy

Cheating WILL be taken seriously. Doing otherwise is not fair to honest students. It is also not fair to allow the cheater to thing that it is a reasonable alternative in life.
Please review the UCSD student handbook for more details on Academic Integrity.
Anyone copying information or having information copied during a test will receive an F for the class and will not be allowed to drop. They will be reported to their college dean. If you can prove non-cooperative copying took place, your grade may be restored, but you must prove it to the dean--I don't want to be involved. Anyone caught cheating or falsely representing the work of others on the homework will not be allowed to turn in further homework. Your grade will be based exclusively on the tests with a penalty of 25% OR GREATER applied.
We photocopy a random sampling of the exams in order to ensure that students do not modify their tests after they have been returned.
Online solutions, etc.: A solutions manual exists for this text. Using it, or any solutions you may find on the internet elsewhere IS CHEATING and will be dealt with accordingly. We know what the solution manual solutions look like. Homework is a small fraction of your grade.

Homework

Homeworks are due by 5.00pm on the due date unless otherwise noted.
Turn in your printed solutions to Sanath's mailbox (Ramesh, Sanath Kumar)in the CSE grad student mailroom, unless otherwise noted.
Late assignments will not be accepted.
There is no regrading of written homeworks, except for addition errors. No single problem will have a significant impact on your grade.
Homework must be completed individually.
Studying in groups is definitely encouraged.
Typically, homework assignments may be graded based on a statistical subset of the problems in each assignment.
Homeworks must be typed or clearly handwritten. Illegible/unreadable answers will receive no credit.

Assignment 1: Discussion Board and Send TA your code name
Assignment 2: Instruction Set Architecture
Assignment 3: x86 and Performance Evaluation
Assignment 4: Performance Evaluation and Single Cycle Processor
Assignment 5: Pipelining and Branch Prediction
Assignment 6: Pipelining
Assignment 7: Cache
Assignment 8: Cache
Assignment 9: Cache

Projects

Project 1: Design Your Own ISA