Announcements:

Xilinx/Verilog Review, 6:30 pm in CSE 4140, January 19.

Related Web Pages:

Lab Assignments

(CSE 141 home page)

There will be a web board for this class, soon. It's a good place to go to look for partners.

Basic Course Information:

• office hours: W 4-5, Th 4-5, F 11-12
• room: B240A
• smazumdar at cs dot ucsd dot edu

• CSB 002, F 2-2:50

There is no textbook for the class, but you will find the CSE 141 textbook helpful in many ways during the lab

Patterson & Hennessy, "Computer Organization and Design -- The Hardware/Software Interface", Morgan Kaufmann, Fourth Edition

The lab will utilize, for some of the lab assignments, the Xilinx ISE Webpack tools. You can dowload a free version of the 11.1 tools from Xilinx here.

Other recommended reading

• Hennesy & Patterson, "Computer Architecture: A Quantitative Approach", 4th edition, Morgan Kaufmann -- a more advanced treatment of many of the same topics in the textbook
• WWW Computer Architecture Home Page -- a comprehensive guide to research and general information on computer architecture available on the web.

Assignments:

• Labs will typically be due two weeks after they are assigned.

Mailing List

The class mailing list will be used by the instructor and the TAs for announcements, etc. All students will be held responsible for announcements and information that go out over the class mailing list. Make sure you are on it. Go here to subscribe to the list.

Grading Information:

• The grade for 141L will be based primarily on 4 lab reports. I expect that most students will complete the lab assignments as specified; thus, the quality of the lab reports will likely be the most important factor in determining grades.  Attendance will also be factored into grades (in a major way) somehow.
• Late assignments are not encouraged. All lab reports are due at the beginning of class on Friday.  Anything else is considered late.  You will have one grace weekend during the quarter. I.e., you can turn one assignment in late, as long as it is in my office (under the door) before 9 a.m. on Monday. I recommend not spending that grace time frivolously early in the quarter. After you have spent your grace days, late assignments will be accepted, but with significant penalties. We will make every effort to return assignments to you in a timely manner -- limiting your ability to turn things in late is, unfortunately, critical to that goal.
• All 4 lab reports are required.  You must do a credible job on each to pass the class.
• We will use gradesource to record lab grades. This will not be a tool to estimate your final grade, etc. It is only there so you can check that we have entered your grades correctly. Please do so -- we don't want to make mistakes.

Integrity:

• Cheating WILL be taken seriously. It is not fair to honest students to take cheating lightly, nor is it fair to the cheater to let him/her go on thinking that is a reasonable alternative in life. Don't test me on this one.
• The following is not considered cheating:
  • discussing the tools or logic design techniques with other groups.
• The following is:
  -Copying lab designs from someone who is not your partner, or lab report text from anyone.
  -Viewing lab designs or lab reports from anyone who is not your partner, including those who have taken the class in previous years.
  -Altering timing data produced by Xilinx, e.g. to make a non-working design appear to be working.

• Penalties -- anyone copying information or having information copied on a lab, or any other violation of class policy, will receive an F in the class and will not be allowed to drop.  They will be reported to their college dean.  If you can prove non-cooperative copying took place, your grade may be restored, but you must prove it to the dean -- I don't want to be involved.

Assignments

• There will be 4 lab assignments. Each will require a written report. There will be no midterms or finals associated with this class. The final grade will be determined by the quality of the lab reports and the completeness and quality of the lab work (as demonstrated in the reports).
• Some but not all of the labs will require the Xilinx tools, which everyone should be familiar with. If you are not, you must take some time the first two weeks to familiarize yourself with it. After that, it will be too late -- you need to be ready to run at that point.
• Most (but not all) of the labs can be done in groups of 1 to 3. Lab reports are to be done collaboratively with your fellow group members, except when specifically instructed otherwise.  Changing, splitting, merging of groups is only to be done with the permission of the instructor, and such permission is typically not given.

Xilinx and Verilog Resources:

Xilinx Schematics tutorial from cse140L Summer 2007
http://www.cse.ucsd.edu/classes/su07/cse140L/140L_tutorial_1_-_summer_2007.pdf
http://www.cse.ucsd.edu/classes/su07/cse140L/140L_tutorial_2_-_summer_2007.pdf

Xilinx Verliog/VHDL tutorial from cse140L Summer 2007
http://www.cse.ucsd.edu/classes/su07/cse140L/140L_tutorial_3_-_summer_2007.pdf

Verilog Overview/tutorial by Sat Garcia
http://www.cse.ucsd.edu/classes/sp07/cse141/slides/vlog-tutorial.pdf
http://www.cse.ucsd.edu/classes/sp07/cse141/slides/verilog_deux.pdf

Verilog Fundamentals by Krste Asanovic at MIT
http://csg.csail.mit.edu/6.375/handouts/lectures/L02-Verilog-Fundamentals.pdf

Verilog Design Examples by Krste Asanovic at MIT (synthesis friendly)
http://csg.csail.mit.edu/6.375/handouts/lectures/L03-Verilog-Design-Examples-1.pdf

At some point, we will attempt to synthesize our circuits (e.g., to extract timing). These resources were selected because they should all be synthesis friendly. Many tutorials and verilog code available on the internet are not.

Lab resources:

• Xilinx Foundation tools are available in CSE B240 and CSE B250. Not sure what version or how up to date. If you go and find out, please let me know.

If you have comments or suggestions, email me at tullsen at cs dot ucsd dot edu