Homework and Projects

Instructor: Michael Taylor

Homework Policies:

• For all homeworks, please create a cover page. The cover page should contain the following info: course (CSE240A), term (Winter 2009), homework number (e.g. HW #1), name(s), and date. To aid in fair grading, please do not put your name(s) on any page other than the cover page.
• You make work on homework in groups of 1 or 2. If working with a group of 2, you only need to submit one writeup. Both members will receive the same grade.
• All homeworks should be submitted to the TA either in person or placed in her mailbox (room 2237 in the CSE building) on or before the deadline. No late assignments will be accepted!
• Typed solutions will make the TA smile but are not strictly required (i.e. please make Chengmo's life easier by typing up your solutions).
• DO NOT submit your homework via e-mail.

Homework:

• Homework 1. Due: Thursday, January 22 at 11am. Solutions.
• Homework 2. Due: Tuesday, February 3 at 11am. Solutions.
• Homework 3. Due: Tuesday, March 10 at 11am. Solutions.

• Project (20% of your grade) - Data Prefetching Competition
• Click here for the project description.
• The project testing results (collected on 32-bit machines) of all the students are here.
• FAQs for the project
• Q1: Can the simulator be installed on a Mac?
  A1: Unfortunately, no. The Prefetch Kit requires some library under linux requirement.
  
  
• Q2: Where can I find a server that provides 100MB+ storage for the project?
  A2: You can use APE machines in the CSE department. All the CSE graduate students can login into these servers using their accounts. For ECE students who do not have CSE accounts, you can submit a request to CSE help to get a temporary account here.
  
  
• Q3: I get errors of "STACK TRACE" when using the trace generator. What is wrong with it?
  A3: There is a problem with the "pin" executable in some versions of the linux kernel. You need to put a flag "-ifeellucky". Try with the following command:

  ../pin/pin -ifeellucky -t ../bin/CMPsim.gentrace32 -threads 1 -o ls.out -- /bin/ls -al

• Q4: What are the block sizes of the L1 and L2 caches?
  A4: The block size for both the L1 and the L2 caches is 64 Byte.
  
  
• Q5: In the sample prefetcher, at every cycle 4 prefetching requests are generated for the L1 cache yet only 1 is generated for the L2 cache. Why?
  A5: This is configured according to the simulator configuration. At one cycle up to four records can be given depending on the number of requests (up to four) issued to the L1 data cache. Therefore at every cycle 4 prefetching requests are generated for the L1 cache in the sample prefetcher. If a requested address misses in the L1 data cache, a request will be placed in the L1 queue. This means that the accesses to the L2 cache at a single cycle depends on the bandwidth of the L1 queue, which is a parameter changed across various configurations. In the 1st configuration, the queue bandwidth is unlimited. In the 2nd and the 3rd configurations, the queue bandwidth is limited to 1. Therefore the sample prefetcher only checks a single request to the L2 cache at every cycle.
  
  
• Q6: When I test the 3rd configuration for the ls program, it seems that prefetching reduces the number of misses, yet increases the CPI. These two factors seem to be contradictory. Why?
  A6: My guess is that the L2 cache is shared by both the IL1 and the DL1 caches. If we prefetch aggressively, the L2 cache will be filled with a lot of prefetched data, while The IL1 blocks in L2 will be kicked out as a result. Therefore we end up having an increasing number of IL1 misses. On the other hand, the number of misses reported on the screen is the L2 miss count for the data part, excluding the instruction part. Therefore the results seem to be contradictory.
  
  
• Q7: Any tips for setting up the project on debian?
  A7: You may need to install zlib1g-dev.
  

   sudo apt-get install zlib1g-dev