Lab 3:

• Here is the Lab 3 description.
• Lab 3 Test sets. In these files you will find two columns. The number in the first column is the value of the memory address (in decimal). The second columnshows what should be in memory at that address. Input is what should be in your test data memory when you start running the program. Output is what should be in your test data memory after running the program. Any memory addresses not listed may have any values in them you care (they are don't cares for us).
  • Set A: Input, Output
  • Set B: Input, Output
• Here is the tutorial on how to build RAMs and ROMs in Xilinx. You can cut and paste to avoid typos. Clearly all the "data" that you store in your RAMs and ROMs will be VERY different and MUCH longer. This is a sample. You also only need to make your memory as big as you need it -- in terms of number of bits to address.
• You must schedule a time for your entire group to meet with a TA to demo your xilinx CPU design. More details will be placed here about what they will expect to see. Please keep checking back.
  Please sign up in lab class or during a TA office hour (for lab) for a time in Week 9 or Week 10.
  • If all group members ABSOLUTELY CANNOT MAKE IT for a demo session, it is the group's responsibility to make sure that member's ideas are represented.
  • You may want to bring your xilinx code installed on your own laptop, as it will probably run faster than the machines in 2444. Otherwise you need to make sure that your files are installedd on a 2444 machine BEFORE your time meeting starts. (ie get there early).
  • You will be expected to show the "running" of both data input sets. Be sure to have both RAMS implemented -- and probably a control value (input to the waveform) to control which RAM to use.
  • You will be expected to answer questions verbally about how different parts of your design work.
• Here are samples from Lab2. They have not changed. Here is a sample schematic and a sample timing diagram. The timing diagram is NOT sufficiently annotated. The schematic is an example of the minimal level of annotation that you should provide. You will produce many schematics and much longer timing diagrams.