Homework

Please remember that homeworks are intended to prepare you for tests. Using any materials other than our textbook to complete homeworks is considered CHEATING. Homeworks must be done individually.

However, you will need to do more than the assigned problems in order ensure you have learned material from class and to prepare for exams and quizzes. Please do the recommended problems as well, and consider meeting with others to dicuss those problems.

NOTE: More recommended problems will be added Week 10. There will be no homework ASSIGNED in Week 10.

Homework Set 8 (due Tues Mar 8 at the beginning of class) -- last one!:

Required: 7.10, 7.33 NOTE: For 7.10 they give WORD addresses -- to get "regular" binary addresses, multiply by 4. So the address stream in binary would be:
8, 12, 44, 64, 84, 52, 256, 192, 76, 44, 14, 88, 16, 108, 24, 44.
Recommended: 7.3, 7.4, 7.5, 7.9, 7.12, 7.14, 7.25, 7.26, 7.27, 7.29, 7.35

Homework Set 7 (due Tues Mar 1 at the beginning of class):

Required: 6.36 a and d only, Q2 (which has 2 parts):
- Q2 (a) give the steady-state CPI of the following code, assuming this loop is executed *many* times. Assume the pipeline from fig 6.41, and a single branch delay slot. Assume nop's do not count as "instructions" in computing CPI.
```
top: add $3, $5, $2 
lw $1, 1000($3) 
sub $2, $7, $1 
sw $2, 2000($3) 
bne $3, $5, top 
nop
```
- Q2 (b) Can you fill the branch delay slot? Which instructions could you use? Give the new CPI if the branch delay slot is filled.
Recommended: 6.36 b and c and also for the correlating branch predictor described in class, 6.27, 6.38, 6.39, start looking at simple Chapter 7 questions.

Homework Set 6 (due Tues Feb 22 at the beginning of class):

Required: 6.18, 6.34
Recommended: 6.19, 6.21, 6.22, 6.26, 6.30, 6.33

Homework Set 5 (due Tues Feb 15 at the beginning of class):

Required: 6.13, 6.4
Recommended: 6.1, 6.2, 6.3, 6.12, 6.14, 6.17, 6.25

Homework Set 4 (due Tues Feb 1 at the beginning of class):
Here are links to figure 5.28 and 5.38 NOTE: 5.38 has an error! in the lw cycle 5 (the circle labelled 4). RegDst should be 0, MemtoReg should be 1. This has been corrected on this picture.

Required:

1) Just like 5.32 - but do addi NOT lui.
- Start from Figure 5.28 on 323. (available for download above) - you will need to print out a copy for each cycle of the instruction!!!! So you will be turning in one copy of 5.28 for EACH cycle required by the addi instruction - label each picture with a stage number and name.
- Highlight or show with pen the active lines of the datapath in each cycle.
- On each cycle, you MUST WRITE the RTL for that stage as well as any comments to explain things.
- You may need to add lines, muxes, and/or new control signals (but maybe not)
- Also print out and modify figure 5.38 (the FSM) on page 339 to show your new control logic
2) Write the microcode sequences for the addi instruction. If you need to make any changes to the field contents, indicate how the new format and fields will control the outputs.

Recommended: 5.28, 5.29, 5.30, 5.32, 5.33, 5.36, 5.38, 5.50, 5.51,5.53

Homework Set 3 (due Tues Jan 25 at the beginning of class):

Required:
- 1) 5.2 a,b,c and 5.3 d,e,f
- 2) This question is similar to question 5.8, but instead I want you to add a jal instruction (jump and link - described on page 79-80 $ra is $31). You must print out or photocopy Figure 5.17 on page 307 and mark it up to show how the datapath now works for all the instructions designed in class and ADDITIONALLY for jal. To do this you may need to add new lines, muxes, or control signals (or maybe not). Also, you should should a new version of the table (5.18) on 308 including the jal instruction. Finally, you must give 2-4 complete English sentences explaining your design decisions.
Recommended: 5.8, 5.9, Like 5.8 but implement addi, 5.11,5.12,5.13, 5,15-5.26

Homework Set 2 (due Tues Jan 18 at the beginning of class):

Required:
- 4.10 This question has 5 questions hidden inside of it, be sure to answer (and put a box around each answer). You MUST use numbers to support your answers. Answers without numbers (and math showing how you got those numbers) get no points.
  - (a) Using C1 on both I1 and I2, how much faster can the makers of I1 claim I1 is compared to I2.
  - (b) Using C2, how much faster can the makers of I2 claim that I2 is compared to I1.
  - (c) If you pruchase I1, which compiler would you use?
  - (d) If you purchased I2, which compiler would you use?
  - (e) Which computer and compiler would you purchase if all other criteria are identical, including cost?
- 4.22 (found on CD -- copied here -- but in the future you may have to get problems off the CD).
  4.22 [5] You are going to enhance a computer, and there are two possible improvements: either make multiply instructions run four times faster than before, or make memory access instructions run two times faster than before. You repeatedly run a program that takes 100 seconds to execute. Of this time, 20% is used for multiplication, 50% for memory access instructions, and 30% for other tasks. What will the speedup be if you improve only multiplication? What will the speedup be if you improve only memory access? What will the speedup be if both improvements are made?
Recommended: 4.1, 4.2, 4.6, 4.8, 4.9, 4.11, 4.14, The amdahl's law questions, 4.25, 4.26, 4.30 (there are many good problems in this chapter), 3.2, 3.5, 3.7, 3.10, 3.30, 3.37

DUE Jan 11! Homework Set 1:

Required:
1) Part A) What addressing modes are supported by MIPS for non-branch instructions? Give a name, brief description, and an actual MIPS instruction example for each one.
Part B) What addressing modes are supported by MIPS for branch instructions? Give a name, brief description, and an actual MIPS instruction example for each one.
2) Decode the following MIPS instructions into assembly language instructions: Hint: Use the MIPS Data Reference Sheet (green) and/or the extra sheet handed out in class.
The break down into groups of 4 is just for readability.
0000 0000 1110 1000 10011000 0010 0000

0010 0001 0000 1001 0000 0000 1111 1111

0000 1000 0000 1100 0000 0000 0000 0001
Recommended: 1.1 through 1.28 (matching), 1.54, 2.3, 2.4
R1) Show the stack, accumulator, and load-store assembly code for the instruction A = X*Y + Y*Z (for the stack assume there is an operation called "dup" which makes a duplicate of the top of the stack (ie pushes another copy of the top of the stack onto the stack).
R2) What are the three basic formats supported by MIPS? For each one give its name and describe it's format telling what information is stored in each bit field. Also give an example of a MIPS instruction that is of that type.