Virtual Lecture for Lab 3:
Finite machine state circuits design
This should give you a decent intro to the parts of lab 3 and let you
get familiar with what each part is asking.
Before we discuss specific parts of the lab, there are a few concepts you should be familar with:
- State Machine: This is a circuit that maintains some sort of internal memory,
where the outputs of the circuit depend at least in part on what condition the
internal memory is in. An example of this would be the shift register from lab 2:
the three outputs all depend on internal memory (the flip flops) as well as the inputs (the shift, clock, and input signals).
Since the output of the adders from lab 2 depends solely on the inputs, the adders were not state machines.
State machines almost always have clocks, so they can read the inputs and change state once each cycle.
- Counter: This is an arrangement of logic that outputs a certain number of bits as a binary number.
Typically it increments or decrements the value it's currently outputting once each clock cycle, and starts over once it
has gone through all of its numbers. Here is six cycles of output from a 2 bit counter: 00, 01, 10, 11, 00, 01.
The counters you'll design and implement in the lab are variations on this idea.
Part 1. A gray code counter
The variation of this part is that instead of cycling directly through binary numbers,
this counter cycles through the gray code equivalent of each binary number. In addition,
whether it increments or decrements its current value depends on the X signal, and it has
to account for the reset signal and set the output to 000 no matter what X says if the reset
signal is 1. When the lab says the counter should not be reset unless the reset signal is
high, it means that the counter should only output 000 if the reset signal is high, if the
current value of the counter is 001 and X is 1, or the current value of the counter is 100 and
X is 0.
During the simulation, you'll probably want to start the counter at 000 (maybe using the
reset signal to hold it there for a couple of cycles) and have it increment 3-5 times. Then
switch X to 1 and have it decrement 8-9 times, then switch X back to 0 and have it increment
until its value is 000 again.
Part 2. 15-second time bomb
This is a fairly straightforward decrementing 4 bit counter. The three inputs mean you'll
have to be careful in defining your state transitions. According to the simulation instructions,
it appears that the start signal is really a "go" signal and should be high (1) the whole time
the counter is going. The stop signal should override the start signal, so that if the stop signal
is high the counter will stay at its current value no matter what start is. The reset signal should
override both, so that if the reset signal is high the counter stays at 15 no matter what the other
inputs are. The blow_up indicator should always stay 0 throughout this until the counter changes from
1 to 0. This means you'll have to worry about making your state transitions safe -- if some combination of
state and inputs besides the specified one makes the blow up signal go high, that's obviously a bad thing.
Part 3. Freeway Traffic Control
This is just a state machine, not a counter (well, maybe it has a 1 bit counter). The states of the machine are
spelled out fairly well in the lab, but I want to note that you'll need a clock in this diagram to tell
your state machine when to switch RED and GREEN lights when cars are waiting in both lanes -- you can
switch the signals once each cycle. Make sure to be very specific on your schematic and simulation which light
is the CARPOOL light and which is the REGULAR light.