In this lab, we will learn how to study and build different types of adders.
Part 1. 4-bit Adder/Subtractor with Overflow. [25pts]
(Please read again the description of this part as it has been changed.)
Build a 4-bit Adder/Subtractor with an Overflow Indicator.
Assume the operands A and B, and the operation result S are all 4-bit 2's complement numbers.
That is, they can count in the range of -8 ... 7. An overflow occurs if the result S is outside of this range.
A 4-bit 2's complement Adder/Subtractor with an Overflow Indicator looks like this:
For this part of the lab, do the following:
| i. | Implement the adder/subtractor with overflow circuit shown above. Explain how it works. |
| ii. |
Simulate the circuit using Xilinx.
Show these 8 simulation cases: 4 + 5, 4 - 3, 6 - 1, 5 + 7, 6 + 3, 6 - 4, 2 + 6, 4 - 6. Note that all operands are positive numbers (e.g. 4, 5). If the simulation case uses a "+", please show an addition. If the simulation case uses a "-", please show a subtraction. Note that the result may be a negative number (e.g. 4 - 6 = -2). Simulation results should include the Overflow output as well. |
Part 2. 4-bit Carry Lookahead Adder. [25pts]
Build a 4-bit carry lookahead adder
| i. | Design and implement the circuit (describe how carry lookahead works and how you derive the final circuit layout) |
| ii. | Build and simulate the circuit using Xilinx. (show the following 8 cases: 15+1, 5+7, 10+5, 2+7, 7+12, 9+3, 2+4, 15+15). |
| iii. | Describe the advantages and disadvantages of carry lookahead adder in relation to ripple adder. Describe in terms of speed (indicate how many levels in the critical path) and area. |
Part 3. 8-bit Carry Select Adder. [25pts]
Build an 8-bit carry select adder
| i. | Design and implement the circuit (describe how carry select adder works and how you derive the final circuit layout) |
| ii. | Build and simulate the circuit using Xilinx (show the following 8 cases: 186+102, 50+151, 114+196, 111+129, 68+29, 213+88, 98+93, 167+106). |
| iii. | Describe the advantage and disadvantage of carry select adder. Describe how many gate levels the critical path contains. |
Part 4. Introducing D Flip Flop. [25pts]
Build a 4-bit shift register using positive edge-triggered D Flip Flops ("FD" in Xilinx).
The next-state table is
Present
StateNext State Shift Q3 Q2 Q1 Q0 0 No Change 1 IL Q3 Q2 Q1
e.g. Let Q3Q2Q1Q0 = 1111, let IL = 0, and let Shift = 1. (Shift = 0 means no change.)
Then the result after shifting is 0111.
| i. | Design and implement the circuit. |
| ii. | Build and simulate the circuit using Xilinx. Show at least 8 clock cycles or data. |
Report
To print simulation waveforms, double click "Simulate Behavioral Model" from the same window you selected "Generate Expected Simulation Results" from. You'll be able to print from the window that pops up (you may want to zoom out or do a zo om full). For simulation waveforms, please order your waveforms alphabetically. Additionally, for outputs related to each other, please use this notation. Consi der the output of a 4bit adder: S3=Most significant bit, S0=Least significant bi t. So, if the result was 3dec = 0011bin, your outputs should be S0=1, S1=1, S2=0 , S3=0. These guidelines help expedite the grading process and are required.
Title page:
- Names of students and due date.
- Title of the lab and objective.
- A brief description of each person's contribution.
- Part 1 i, ii
- Part 2 i, ii, iii
- Part 3 i, ii, iii
- Part 4 i, ii
- Xilinx printouts of all schematics generated in this lab. Printouts of all Simulation waveforms must also be included. Busses are required for inputs and outputs (values you would enter into the simulator). Simulations should be generated by using the Generate Expected.. Take screen shots of your waveforms and integrate these into your report.
- Include this printout at the end of the lab report
90% will based on the completeness and correctness of the report. 10% will based on the neatness, organization, and following instruction of the report format.