CSE Department
University of California, San Diego

CSE 140 - Winter 2004

Components and Design Techniques
for Digital Systems


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Instructor

Prof. Alex ORAILOGLU

Office hours (APM' 4840) : Tuesdays 11:00 am - 12:00 noon
Thursdays 4:00 pm - 5:00 pm
E-mail: alex@cs.ucsd.edu

Teaching Assistants

Head TA : Ozgur SINANOGLU
Office hours (APM' 4819) : Wednesdays 1:30 pm - 3:30 pm
E-mail: ozgur@cs.ucsd.edu
Baris ARSLAN

Office hours (APM' 4819) : Tuesdays 2:30 pm - 4:30 pm
Wednesdays 10:30 am - 12:30 pm
E-mail: barslan@cs.ucsd.edu

Class Schedule

Lecture: Mondays and Wednesdays 5:00 pm - 6:20 pm; Room: CENTR 109
Discussion Session: Thursdays 5:00pm - 6:20pm; Room: CENTR 105; Attendance is required!

Course Material to Download

Textbook :
Principles of Digital Design, by Daniel D. Gajski, Prentice Hall, 1997. ( Available in the reserve section of the Undergraduate library)
ERRATA:
  • Fig 2.10 part C: excess 1032 should be excess 1023.
  • Fig. 3.3: xi, yi -> si delay should be 7.6, NOT 7.2
  • Fig. 3.4 xi, yi -> ci+1 delay should be 3.2, NOT 4.2
  • Fig. 3.5 AOI 3-wide, 2-inputs, marked delay on the schematic should be 2.2 not 2.0 Consequently all 4.4 ns delay paths in summary should also be 4.6
  • Page 144, QM tables, subcubes (8,9) should be 1 0 0 _ instead of _ 0 0 1. Similarly, subcubes 9,13 and 13,15 have the same mistakes of wrong placement of the dash.
  • Table 5.2: The delays marked as x0,y0 are actually from any x,y input, the worst case delay actually comes from x3,y3 because the generate signal for the CLA block does not depend on the propagate signal of x0,y0.
  • Table 5.2: x0,y0 -> c8 delay should be 15.8, NOT 16.2
  • Table 5.2: x0,y0 -> c12 delay should be 16.6, NOT 17

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    Exam Dates and Evaluation

    Midterm 1 : January 28, 2004 ( 25% ) ( Avg: 63.0 Median: 64.0 S.D.: 16.44 )
    Midterm 2 : February 18, 2004 ( 25% ) ( Avg: 60.4 Median: 61.0 S.D.: 16.22 )
    Final : March 18, 2004, 7:00 - 10:00 pm ( 50% )
    Pop Quizzes: Unannounced ( 2% each )