CSE 142 Advanced Digital Logic Design

 

NEWS:

Solutions (first draft--could be off by a few bits...) to the third homework are here.

Office hours will be on Wednesday (4-5 as usual) and Monday (11:00 AM - 11:50 AM).

Review session for the Final Exam will be on Tuesday (18th) from 5-7 in HSS 2152.

Some notes about flow-tables are here.

Solutions (now even better!) to the second homework are here.

Extra office hours this week on Monday from 4-5 in the same room. Review session on Tuesday from 5-7, room to be determined.

Homework 2 and Midterm 2 have both been delayed for 1 week.

Solutions to the first homework are here. They're ASCII text (with ASCII-art k-maps...) so use an equal-width font to view them (like Courier).

I'm holding extra office hours on Monday PROBABLY from 4-5, possibly in a different room. I'm holding a review session on Tuesday PROBABLY from 5-7. I'm still coordinating with the administration on those things.

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Discussion sections are on Fridays from 1:00 to 1:50 in 104 Peterson (same room as lecture).


Instructor:

Prof. Arthur Friedman
friedman@cs.ucsd.edu

TA:

Andrew Smith
atsmith@cs.ucsd.edu
Office Hours: Wednesday 4:00 - 5:00 3349A AP&M

If you have specific questions, please email me in advance so I can figure out the answers (as opposed to making up something that sounds good). If you can't make my office hours send me an email.


Course Outline:

I. Review (1 week)
II. Combinational Functions, Special Properties (3 weeks)
III. Asynchronous Sequential Circuit Design (3 weeks)
IV. Digital Circuit testig & Reliable Design (3 weeks)


Grading Standards:

Midterm I 25%
Midterm II 25%
Final 50%

Homeworks may influence borderline grades.


Important Dates:

1/31/03 Homework 1 due
2/6/03 (tenative) Midterm 1
2/14/03 Homework 2 due
2/20/03 (tenative) Midterm 2
3/14/03 Homework 3 due
3/18/03 Final Exam