CSE 141L -- Computer Architecture Lab
Winter 2002, Instructor: Dean Tullsen
Announcements:
[NEW] TA Brian Boozer has done a great job creating this
tutorial on how to use some useful and necessary features of Xilinx.
Lab
Assignments
(CSE
141 home page)
Basic Course Information:
-
Instructor: Dean
Tullsen
-
TA: Brian Boozer
-
TA: Matt Clothier
-
Consulting TA: Tim Pevzner
-
Meeting times and places
-
Course textbooks and tools
-
There is no textbook for the class, but you will
find the CSE 141 textbook helpful in many ways during the lab
-
Patterson & Hennessy, "Computer Organization
and Design -- The Hardware/Software Interface", Morgan Kaufmann, Second
Edition
-
The lab will utilize, for some of the lab assignments,
the Xilinx foundation tools (version 2.1).
-
Other recommended reading
-
Assignments:
-
Labs will typically be due two weeks after they are
assigned.
-
Once it is set up, the class mailing list will be
used by the instructor and the TAs for announcements, etc. All students
will be held responsible for announcements and information that go out
over the class mailing list. Make sure you are on it. To sign up
for the mailing list, send mail to listserv@ucsd.edu, with a blank subject
and one line in the body: add my_email_address cse141lab-l
-
You can use the mailing list to ask general questions
(e.g., problems/questions with the tools), within reason. If you
are not sure whether a question is appropriate for the mailing list, you
can forward to the instructor and ask.
Grading Information:
-
The grade for 141L will be based solely on 4 lab
reports. I expect that most students will complete the lab assignments
as specified; thus, the quality of the lab reports will likely be the most
important factor in determining grades.
-
Late assignments are not encouraged. All lab reports
are due at the beginning of class on Wednesday. Anything else is
considered late. You will have one 2-day grace period during the
quarter. I.e., you can turn one assignment in late, as long as it is in
my office (under the door) before 9 a.m. on Friday. I recommend not spending
that grace time frivolously early in the quarter. After you have spent
your grace days, late assignments will be accepted, but with significant
penalties. We will make every effort to return assignments to you in a
timely manner -- limiting your ability to turn things in late is, unfortunately,
critical to that goal.
-
All 4 lab reports are required. You must do
a credible job on each to pass the class.
Integrity:
-
Cheating WILL be taken seriously. It is not fair
to honest students to take cheating lightly, nor is it fair to the cheater
to let him/her go on thinking that is a reasonable alternative in life.
Don't test me on this one.
-
The following is not considered cheating:
-discussing the tools or logic design techniques
with other groups.
-
The following is:
-Copying lab designs from someone who is not
your partner, or lab report text from anyone.
-Viewing lab designs or lab reports from
anyone who is not your partner, including those who have taken the class
in previous years.
-Altering timing data produced by Xilinx, e.g.
to make a non-working design appear to be working.
-
Penalties -- anyone copying information or having
information copied on a lab will receive an F in the class and will not
be allowed to drop. They will be reported to their college dean.
If you can prove non-cooperative copying took place, your grade may be
restored, but you must prove it to the dean -- I don't want to be involved.
Assignments
-
There will be 4 lab assignments. Each will require
a written report. There will be no midterms or finals associated with this
class. The final grade will be determined by the quality of the lab reports
and the completeness and quality of the lab work (as demonstrated in the
reports).
-
Some but not all of the labs will require the Xilinx
tools, which everyone should be familiar with.
-
Most (but not all) of the labs can be done in groups
of 1 to 3. Lab reports are to be done collaboratively with your fellow
group members, except when specifically instructed otherwise. Changing,
splitting, merging of groups is only to be done with the permission of
the instructor, and such permission is typically not given.
-
Lab resources:
Xilinx Foundation tools are available in
-APM 2444 and EBU2 315
-personal copies of Xilinx are available through
the bookstore.
Suns will be available in the uAPE lab in the AP&M
basement.
If you have comments or suggestions, email me at
tullsen@cs.ucsd.edu