CSE 141 Ungraded Homework #5

Recommended "due date" - March 8.

  1. Suppose we have a (very small) direct mapped, write-allocate, write-back cache that can hold two blocks of 8 Bytes each. The cache is initially empty. The following sequence of memory operations are made, where each reference is a byte address of a 4-byte number: Load 0, Store 44, Load 52, Load 88. At this point, which memory references will result in cache hits? (Only conside word aligned word addresses, i.e. locations 0, 4, 8, and so on.)

  2. Which cache blocks (if any) are "dirty"?

  3. Suppose the memory operations continue as follows. Indicate which references are hits, which are "clean" misses where no write-back is required, and which are dirty misses requiring a write-back operation.

    Load 0

    Store 52

    Load 68

    Load 44

  4. My favorite computer has a 4-way set associative cache which can hold 512 blocks, each block being 128 Bytes long, a 2-way set associative TLB with 64 entries, a page size of 4096 Bytes, 32-bit virtual addresses, and 28-bit real addresses. The cache is physically addressed and memory references use byte addressing. Describe in detail the steps involved in processing a load instruction which results in a cache and TLB hit. Your description should tell exactly which bits of the physical and virtual addresses are used for each step, how long the tags are, and so on. (Draw pictures if you think they will help your explanation.)

  5. Now describe what would happen differently if the instruction were a cache miss and TLB miss.