CSE 291: Topics on High Performance Processor Architectures
Winter Quarter, 2001 (1 or 4 credits)
Time: TuTh 3:55-5:15, Place: AP&M 4218
Instructor: Dean
Tullsen
Office Hours: by appt.
Announcements:
Reading list:
January 9: Intro (Dean)
January 11: Slipstream Processors (Dean)
A
Study of Slipstream Processors
Z. Purser, K. Sundaramoorthy, E. Rotenberg (North Carolina State University)
January 16: Barbara
Speculative
Data-Driven Multithreading
Amir Roth and Gurindar Sohi, University of Wisconsin at Madison
Register
Integration: A Simple and Efficient Implementation of Squash Re-Use
A. Roth, G. S. Sohi (University of Wisconsin - Madison)
January 18: Karim
PipeRench
Implementation of the Instruction Path Coprocessor
Y. Chou, P. Pillai, H. Schmit, J. P. Shen (Carnegie Mellon University)
Research Update -- Tim Sherwood
January 23: ??
Symbiotic
Jobscheduling for a Simultaneous Multithreading Processor
Allan Snavely, Dean Tullsen (University of California, San Diego)
An
Analysis of Operating System Behavior on a Simultaneous Multithreaded Architecture
Joshua Redstone, Hank Levy, Susan Eggers (University of Washington)
January 25: Tim
Data-flow
Prescheduling for Large Instruction Windows in Out-of-Order Processors
Pierre Michaud and André Seznec, IRISA/INRIA
Research Update -- ?
January 30: Jeff
Eager
Writeback - a Technique for Improving Bandwidth Utilization
H.-H. Lee, G. S. Tyson (University of Michigan), M. Farrens (University
of California, Davis)
Silent
Stores for Free
K. M. Lepak, M. H. Lipasti (University of Wisconsin - Madison)
February 1: Eric
Instruction Distribution
Heuristics for Quad-Clustered, Dynamically-Scheduled, Superscalar Processors
A. Baniasadi (Northwestern University), A. Moshovos (University of
Toronto)
Research Update -- Eric
February 6: Jamison
Dynamic Branch
Prediction with Perceptrons
Daniel Jimenez and Calvin Lin, University of Texas at Austin
Branch
History Guided Instruction Prefetching
Viji Srinivasan, Edward Davidson, Gary Tyson, Mark Charney, and Thomas
Puzak, University of Michigan and IBM T.J. Watson Research Center
February 8: Roger
Reducing DRAM
Latencies with an Integrated Memory Hierarchy Design
Wei-fen Lin, Steven Reinhardt, and Doug Burger Universities of Michigan
and Texas at Austin
Research Update -- ?
February 13: Karim
Performance Improvement
with Circuit-Level Speculation
T. Liu, S.-L. Lu (Intel)
DRAM
Energy Management Using Software and Hardware Directed Power Mode Control
Victor Delaluz, Mahmut Kandemir, Vijaykrishnan N., Anand Sivasubramaniam,
and Mary Jane Irwin, Penn State University
February 15: Eric
Designing
Computer Systems with MEMS-based Storage
David Nagle, Steven Schlosser, John Linwood Griffin, Gregory Ganger
(Carnegie Mellon University)
Research Update -- ?
February 20: Peter
Architectural
Support for Copy and Tamper Resistant Software
David Lie (Stanford University), Chandu Thekkath (Compaq Systems Research
Center), Patrick Lincoln (SRI International), Mark Mitchell (Stanford University),
Dan Boneh (Stanford University), John Mitchell (Stanford University), Mark
Horowitz (Stanford University)
On
Pipelining Dynamic Instruction Scheduling Logic
J. Stark (Intel), M. D. Brown, Y. N. Patt (University of Texas at Austin)
February 22: Jamison
Two-level
Hierarchical Register File Organization for VLIW Processors
J. Zalamea, J. Llosa, E. Ayguade, M. Valero (Universitat Politecnica
de Catalunya)
Research Update -- ?
February 27: Judy
A Static Power Model
for Architects
J. A. Butts, G. Sohi (University of Wisconsin - Madison)
A
Framework for Dynamic Energy-Efficiency and Temperature Management
W. Huang, J. Renau, S.-M. Yoo, J. Torrellas (University of Illinois
at Urbana-Champaign)
March 1: John
Dynamic Thermal
Management for High-Performance Microprocessors
David Brooks and Margaret Martonosi, Princeton University
Research Update -- John
March 6: Roger
Memory
Hierarchy Reconfiguration For Energy And Performance In General-Purpose
Processor Architectures
R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, S. Dwarkadas (University
of Rochester)
Frequent
Value Compression in Data Caches
J. Yang, Y. Zhang, R. Gupta (University of Arizona)
March 8: Judy
Reducing
Wire Delay Penalty through Value Prediction
J.-M. Parcerisa, A. Gonzalez (Universitat Politecnica de Catalunya)
Research Update -- Barbara
March 13: Projects (?)
March 15: Projects
Unscheduled Papers
(Micro)
Predictor-Directed Stream Buffers
T. Sherwood, S. Sair, B. Calder (University of California, San Diego)
Relational Profiling: Enabling Thread Level Parallelism in Virtual Machines
T. H. Heil, J. E. Smith (University of Wisconsin - Madison)
(HPCA)
"Performance of Hardware Compressed Main Memory"
Bulent Abali, Hubertus Franke, Xiaowei Shen, Dan E. Poff, and
T. Basil Smith, IBM T.J. Watson Research Center
"Dynamic Prediction of the Critical Performance Path"
Eric Tune, Dongning Liang, Dean Tullsen, and Brad Calder, UCSD
ASPLOS
Efficient and Flexible Value Sampling
Michael Burrows (Compaq SRC), Ulfar Erlingson (deCODE Genetics), Shun-Tak
Leung (Compaq SRC), Mark Vandevoorde (AltaVista), Carl Waldspurger (VMWare),
Kip Walker (CMU), Bill Weihl (Akamai)
OS and Compiler Considerations in the Design of the IA-64 Architecture
Rumi Zahir (Intel Corporation), Jonathan Ross (Hewlett Packard Company),
Dale Morris (Hewlett Packard Company), Drew Hess (Lucas Digital Ltd.)
Hardware Support for Dynamic Management of Compiler-Directed Computation
Reuse
Daniel Connors, Hillery Hunter, Ben-Chung Cheng, Wen-Mei Hwu (UIUC)
Software Profiling for Hot Path Prediction: Less is More
Evelyn Duesterwald, Vasanth Bala (Hewlett Packard Labs)
tullsen@cs.ucsd.edu