Changelog

Part 1: Log into the discussion board

Due: August 7

There is a link to the course's discussion and announcement board on the course homepage. Sign up for them.

Take some time to explore the discussion boards features.

Reading the discussion forum is mandatory. It is the only place that all announcement related to class will be posted.

Due: August 7

Lab 1 is a preparation stage for future labs, and consists of two parts - Altera Quartus and Verilog. In Lab 1, you will install the Altera tools and follow a step-by-step tutorial to learn essential concepts and working flow in hardware designs. For those who used Altera Quartus in 140L, this lab should be very easy. Otherwise, you should START NOW - there might be many unexpected problems. If you have any question regarding this lab, please post it on the discussion forum.

Please follow the course coding standards for verilog here (special Thanks to 2012 Winter CSE141L staff).

Tools:

The main verilog development tools we use in this class are Altera's Quartus II Web Edition (version 12.0sp1) and ModelSim-Altera Starter. Both of these tools should already be on the lab machine. If you would like to install them for personal use (laptops, home desktops, etc.) here some instructions for downloading the tools:

• Get Altera Quartus II Web Edition 12.1sp1. Note: It should already be installed in the labs. Please let use know if you find machines that do not have the software, or have older versions.

  1. Go to this link.

  2. Select the Windows link (Linux tools are available but we will not be supporting them in this class).

  3. If you already have an account with Altera, put your username and password. Otherwise, use the One-Time Access option.

  4. Altera uses a download manager to speed up the download, you can use that, or click on the download your file now link at the bottom. The download is ~3 GB and will take a while to download.

  5. Run the downloaded file to install the web edition tools. Click through the installation with all of the default options. You do not need to get a Quartus II subscription license, so uncheck the box on the last screen of the installer.

• Get ModelSim-Altera Starter 6.6d. This also should be installed on the lab machines.

  1. Go to this link.

  2. Select the Windows link from Option 2 (See note above about linux support). We've found that the installers from option 1 don't always work.

  3. If you already have an account with Altera, put your username and password. Otherwise, use the One-Time Access option.

  4. Altera uses a download manager to speed up the download, you can use that, or click on the download your file now link at the bottom. The download is 300-700 MB.

  5. Run the downloaded file to install the tool. Click through the installation with all of the default options.

Altera Quick Tutorial

Altera provides a good step-by-step tutorial. With this tutorial, you will be able to learn how to perform various activities in the hardware design process. It should take less than two hours to follow the tutorial.

• Open the Altera quick tutorial .

• Follow instructions in the tutorial, up to and including Section 6.1. You will design and compile a simple light controller circuit in Verilog. When creating your project, target the DE1 board with the 'Cyclone II EP2C20F484C7' FPGA.

• Try to understand the Verilog source file used in the tutorial.

• Also work through the first three chapters of the ModelSim tutorial. You can get a copy of the example files for this tutorial here.

• A consolidated tutorial on Modelsim simulation can be found here.

A Simple 8 bit Adder

Now that you know how to use Altera Quartus II, we will examine a few aspects of hardware design.

• Suppose that you got a job from 'San Diego Chip Factory'. Your boss gave you an adder design written in Verilog - adder.v to implement it in an Altera FPGA 'Cyclone II EP2C20F484C7'. Your first assigned task is to understand the source file thoroughly, and make a project in Altera Quartus II.

• To see what is really going on, perform a behavioral simulation in Modelsim. You should use this as a starting point: test_adder.v.

• You need to modify the Testbench to give the proper stimulus and make sure the clock will run at 500MHz (Hint : t=[1/f] and clock toggles every t/2).

• Simulate for the following sets of inputs:

• One input is consecutive 8 bit odd numbers and other is consecutive 8 bit even numbers. For example, 1 + 2, 3 + 4, 5 + 6 etc. Your testbench should generate a new pair of inputs for every clock cycle.

• Try a pattern which can give you both even and odd numbers as the sum. Does your adder behave as you expected?

• You might have noticed that output isOdd is updated one cycle later than out. Modify the adder verilog file so that isOdd is simultaneously updated with out. Perform the same behavioral simulation you did in the previous step again.

• After you checked your adder is functionally correct, it is time to synthesize. In the synthesize stage, Altera Quartus translates your Verilog design to what its backend stage (implementation stage) can understand. To synthesize a design, just double-click "Analysis and Synthesis" in the Tasks pane. Skim through the generated synthesis report.

• Now you'll want to see how your design maps onto the FPGA. The stage where the design tools find a good layout on the device is called "Place and Route". Run this stage by double clicking on "Fitter" in the Tasks pane. Skim through the generated reports.

• Now that the design tools have mapped your design to an FPGA, you can estimate timing and figure out how fast your adder will operate. Run the design through the whole compilation chain, which includes a timing analysis: go to the "Processing" menu, click "Start Compilation." Look over the reports in the "TimeQuest Timing Analyzer" section. The Fmax number in "Slow Model" Report is the maximum clock frequency at which your adder will run. The "Slack" and "TNS" indicate how well the design meets the timing constraints in the clock domain. These can be seen in each of the "Setup Summary" reports. For more information on timing analysis in Quartus II, see the tutorial on timing.

• To show your boss that your adder would work at a certain frequency, you need to do a post-route simulation with the same testbench in Question 2. Sometimes, post-route simulation is also used to verify the validity of your implementation. (The result of post-route simulation should tally with that of the behavioral simulation.) Running a post-route simulation is very similar to running a behavioral simulation. Since the tutorials do not cover how to run a timing simulation using ModelSim and a Verilog testbench, here are the instructions you'll need to get started:

1. Make sure you have the simulation tool settings set to Modelsim in Quartus II. To do this

   • Open settings from EDA Netlist writer -> Edit Settings

   • Navigate to EDA Tools Settings -> Simulation and select "ModelSim-Altera" under "Tool Name"

   • Make sure your output format is "Verilog HDL" instead of VHDL!

   • Click on "OK" to apply the settings

2. Make sure to run the entire compilation process in Quartus II (including "EDA Netlist Writer")

3. Open ModelSim

4. Select "File" - "Change Directory..." and navigate to the "simulation" and then "modelsim" subdirectories under your adder project directory. If you forget to do this you will likely end up with the error "SDF file was not found" when you run your simulation.

5. Select "File" - "New" - "Library..." and select "a new library and a logical mapping to it." Name the library "work" and enter "work" for the library physical name as well. You should then see the work library at the top of the library list.

6. Select the work library and select "Compile" - "Compile..." Select adder.vo (assuming your project name in Quartus was set to "adder") and then click "Compile." Then navigate to test_adder.v (the same testbench as before), which should be a couple directories up. Click "Compile" with test_adder.v selected. THen click "Done". Now, in the library list, if you expand the "work" library, you should see "adder" and "test_addr". In the future, if you make any changes to adder or testbench Verilog source, you'll need to recompile the "work" library before re-simulating.

7. Select "Simulate" - "Start Simulation" and do the following:

• In the "Design" tab, expand the "work" library and highlight "test_adder". Select "ns" in the "Resolution" drop-down field.

• In the "Libraries" tab, in the "Search Libraries" area, select "Add" and add the "cycloneii_ver" library.

• In the "SDF" tab, select "Add". Add adder_v.sdo and apply it to the region /test_adder/dut.

• Finally, click on "OK" to start the simulation. After this, use ModelSim to run the timing simulation in the same manner you used it to run the functional simulation.

32 bit Adder

• Now that your adder works fine, your boss wants you to extend your adder to support 32bit additions. Modify your verilog source file, synthesize it, and implement it. (Hint: You can very easily extend the existing 8bit adder to 32bit.)

• Generally, the more complex and the bigger a design is, the slower it is. Two important causes are: (1) more complex logics usually use more LUTs, thereby increasing their logic delays, (2) as a design gets bigger, it is increasingly difficult to place and route LUTs in their optimal places.

Useful Resources

• All Altera Tutorials