Follow this link to the CSE 140L Webpage
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CSE 140 Summer 2011 (Tu/Th: 5:00 - 6:20 pm, WLH 2111) |
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Instructor: |
Alex Orailoglu, alex@cs.ucsd.edu EBU3B 3134 |
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Discussion Section Monday and Wednesdays 6:30-7:50 PM EBU3B 2154 |
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Tutor: |
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Raymond Paseman |
Office Hours Tuesdays and Wednesdays 11:00 AM - 12:30 PM Thursday 11:00AM - 12:00 PM EBU3B B240A |
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Text Book: Principles of Digital Design, by Daniel D. Gajski, Prentice Hall, 1997. Available in the reserve section of the undergraduate library.
Midterm: July 19, 2011, 5:00 - 7:50 PM, EBU3B 2154 Final: June 9, 2011, 7:00 -- 10:00 PM EBU3B 2154
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*Please check back frequently to see the updated announcements. |
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Homeworks: |
Link to WebCT: http://ted.ucsd.edu/ Please read the tutorial on how to turn your homeworks
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Errors in the text book: |
1. Fig 2.10 part C: excess 1032 should be excess 1023 2. Fig. 3.3: xi, yi -> si delay should be 7.6, NOT 7.2 3. Fig. 3.4 xi, yi -> ci+1 delay should be 3.2, NOT 4.2 4. Fig. 3.5 AOI 3-wide, 2-inputs, marked delay on the schematic should be 2.2 not 2.0 Consequently all 4.4 ns delay paths in summary should also be 4.6 5. Page 144, QM tables, subcubes (8,9) should be 1 0 0 _ instead of _ 0 0 1; subcubes (9,13) should be 1 _ 0 1 instead of 1 0 _ 1; subcubes (13,15) should be 1 1 _ 1 instead of 1 _ 1 1. Figure 4.18 (d), the prime implicant expression of P2 should be wx'y' instead of x'y'z; the prime implicant expression of P4 should be wy'z instead of wx'z; the prime implicant expression of P6 should be wxz instead of wyz. Corresponding changes of the expressions should also be made in the PI list, EPI list and Cover lists in Figure 4.18(e), as are done in your Chapter 4 handout 6. Table 5.2: The delays marked as x0,y0 are actually from any x,y input, the worst case delay actually comes from x3,y3 because the generate signal for the CLA block does not depend on the propagate signal of x0,y0 7. Table 5.2: x0,y0 -> c8 delay should be 15.8, NOT 16.2 8. Table 5.2: x0,y0 -> c12 delay should be 16.6, NOT 17
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