Follow this link to the CSE 140L Webpage

CSE 140 Summer 2009 

(Tu/Th: 5:00 - 7:50 pm, EBU3B 2154)

 

Instructor:

Alex Orailoglu, alex@cs.ucsd.edu

Office Hours:
Tuesdays and Wednesdays 3:30 -- 4:30 pm;

EBU3B 3134

Teaching Assistants

Chengmo Yang

c5yang@cs.ucsd.edu

Office Hours

Mondays and Wednesdays 11:30 am -- 1:00 pm, Tuesdays 1:00 -- 2:30 pm;

EBU3B B240A

 

 

 

Discussion Section: Mondays and Wednesdays 6:30 - 8:00 pm; EBU3B 2154

Text Book: Principles of Digital Design, by Daniel D. Gajski, Prentice Hall, 1997. Available in the reserve section of the undergraduate library.

Handouts:
  1. Course Info
  2. Course Policy
  3. Course Contents
  4. Multiplication and division
  5. IEEE 754 number representation
  6. Error detection and correction
  7. Quine McCluskey

Midterm: 07/21/2009, 5:00 -- 7:50 pm
Final: 08/01/2009, 7:00 -- 10:00 pm

Evaluation:

 

%

Midterm

40%

Final

45%

Homeworks

15%

 

 

Announcements:
*Please check back frequently to see the updated announcements.

*Chengmo will give the lecture on Tuesday (06/30) and Thursday (07/02). No discussion section on either Monday (06/29) or Wednesday (07/01).

*Alex will give two make-up lectures on Monday (07/06) and Wednesday (07/08) using the discussion sections.

*Alex will not hold office hours this Tuesday (06/30) and Wednesday (07/01).  

*Please read the tutorial on how to turn your homework
 Link to WebCT: http://webct.ucsd.edu/

 

 

Homeworks:
  1. HW1 Due July 13, 2009 (Mon) at 3pm
  2. HW2 Due July 20, 2009 (Mon) at 3pm
  3. HW3 Due July 31, 2009 (Fri) at 3pm

 

 

Errors in the text book:

1.        Fig 2.10 part C: excess 1032 should be excess 1023

2.        Fig. 3.3: xi, yi -> si delay should be 7.6, NOT 7.2

3.        Fig. 3.4 xi, yi -> ci+1 delay should be 3.2, NOT 4.2

4.        Fig. 3.5 AOI 3-wide, 2-inputs, marked delay on the schematic should be 2.2 not 2.0 Consequently all 4.4 ns delay paths in summary should also be 4.6

5.        Page 144, QM tables, subcubes (8,9) should be 1 0 0 _ instead of _ 0 0 1; subcubes (9,13) should be 1 _ 0 1 instead of 1 0 _ 1; subcubes (13,15) should be 1 1 _ 1 instead of 1 _ 1 1.  Figure 4.18 (d), the prime implicant expression of P2 should be wx'y' instead of x'y'z; the prime implicant expression of P4 should be wy'z instead of wx'z; the prime implicant expression of P6 should be wxz instead of wyz. Corresponding changes of the expressions should also be made in the PI list, EPI list and Cover lists in Figure 4.18(e), as are done in your Chapter 4 handout

6.        Table 5.2: The delays marked as x0,y0 are actually from any x,y input, the worst case delay actually comes from x3,y3 because the generate signal for the CLA block does not depend on the propagate signal of x0,y0

7.        Table 5.2: x0,y0 -> c8 delay should be 15.8, NOT 16.2

8.        Table 5.2: x0,y0 -> c12 delay should be 16.6, NOT 17