Due Thursday, August 24th at the beginning of class.
In this project, you will design the ALU (arithmetic logic unit) and the internal storage of your CPU. You will implement your design in LogicWorks, where you will connect the parts together and demonstrate that they work through schematic diagrams and timing printouts.
By "internal storage", we mean the register file, stack, accumulator, or whatever similar structure your ISA relies on. If your ISA has none of these, or if your machine operates completely out of memory, you will have to rig up something to supply operands to the ALU in order to demonstrate it. For the rest of this document, we'll refer to the internal storage as "the register file", for simplicity.
You should connect your register file to your ALU in a manner similar to that shown in the attached schematic.
In this schematic, the ALU has two 8-bit inputs (A and B), one 8-bit output (C), and three control bits (OC). The ALU is a combinational logic block: it computes the output C, as a function of the inputs A and B, with the function selected by the control bits. With three control bits, the ALU can support eight different functions, though it may implement fewer. In this example, we've shown control inputs (ALU "op codes") for eight different functions. Your ALU and ISA will likely support different functions, and use different ALU control bits to select them.
This sample register file has two 8-bit data outputs (DOA, DOB), and one 8-bit data input (DI). The register file also has three address inputs: RAA ("Read Address A"), RAB ("Read Address B"), and WA ("Write Address"). Finally, there are the "write enable" and clock signals. The register file continuously retrieves the values of the registers addressed by RAA and RAB, and drives those values on the data outputs DOA and DOB. The register file may also write to up to one register per cycle: at a positive clock edge, if the "write" signal is active, the value at the data input DI is copied into the register addressed by WA. Note that, since this register file uses two bits for addressing, it contains a maximum of four registers.
Besides the ALU and register file, there are LogicWorks hex entry pads, a few switches, and a big multiplexer. The hex entry blocks allow you to manually select register addresses, ALU opcodes, and enter data values. The multiplexer is used to manually write values into the register file in order to demonstrate your data path, without having to re-wire the circuit.
This entire circuit is just a sample. Yours will differ, especially in the ALU operations supported, the bit-patterns you use to encode them, the number of registers addressed, etc. (Note: the specific figure and timing diagram shown were prepared with an earlier version of LogicWorks.)
As part of this project, you will provide detailed LogicWorks schematics (printed on paper). In addition to your top-level testing circuit, which will look something like the sample, you must also show all internal circuits used in your design: your ALU implementation, your register file, etc. (Note: you may not use any of the VHDL features offered by LogicWorks.)
You are strongly encouraged to use the LogicWorks features which allow you to collect circuitry into a block, and then re-use that block in other circuits. In the example circuit, observe that the ALU is shown as a module, instead of directly as a multitude of gates. The implementation of the ALU is a separate diagram, showing only the internals of the ALU; within the ALU, the adder itself might be a module containing a sub-circuit. Organizing your circuitry in a hierarchy like this is akin to using subroutines in software development: it helps you manage complexity, and can make your system much easier to understand.
In addition to providing schematics, you must demonstrate correct operation of all of your ALU operations using LogicWorks timing diagrams (printed on paper). An example of a partial timing diagram is included; yours will have more detail.
The timing diagram should demonstrate all ALU operations (this includes math to support load/store address computation and branch target computation, but not PC incrementing), each with a couple of interesting inputs. Make sure that "corner cases" (unusual inputs) are demonstrated, if relevant.
The timing diagram should also demonstrate all of the functionality required of your internal storage, such as writing ALU outputs to registers, and reading different registers. In particular, you should demonstrate that you can use the same register as a source and destination operand of the same instruction, if allowed by your ISA.
The schematics and timing diagrams will be difficult for us to understand without a great deal of annotation: add notes telling us what's going on. Good organization and use of hierarchical design also help. (If we can't understand it, we'll assume it doesn't work.)
You must turn in a project report, printed on paper, in addition to your printed schematics and annotated timing diagrams. Be sure to list the names of everyone in your group on the report. Groups are expected to be the same as those used in the first project; changes must be approved in advance.
Your writeup is to be organized as follows. Be sure to answer all questions: