CSE 140L - Digital Systems Lab

Summer 2006

Class

Friday: 9:00am - 11:50am, Center 201

Course Description

This course covers topics in the design of digital circuits. The majority of the class is devoted to small digital design projects. This course also provides an introduction to hardware design tool called Xilinx Webpack and ModelSim.

Textbook

Not required. Professor recommend the following book:
"Digital Design: Principles & Practice", John F. Wakerly, Prentice Hall

Instructor

Isaac Chu, UCSD Guest Lecturer, Systems Architect
ichu@ece.ucsd.edu
Office hours:  S&E library study room

                      Friday 1:00 pm - 5:00 pm

 

Teaching Assistant

Raid Ayoub:  rayoub@cs.ucsd.edu
Office hours:  EBU3B B270

                      Wednesday: 10:00 am – 12:30 pm

                      Thursday:     5:00 pm – 8:30 pm

 

Haikun Zhu:  hazhu@cs.ucsd.edu

Office hours:  EBU3B B270

                      Tuesday :  2:00 pm – 4:00 pm

    

Lab Assignments

Lab 1 (due week 2): gray-code enconder/decoder, 7-segment display
Lab 2 (due week 3): adder/subtractor, carry-lookahead adder and carry-select adder
Lab 3 (due week 4): state machine circuits (counter, traffic light controller)
Lab 4 (due week 5): introduction to CPU design (mini-CPU)

Course Plan

Week 1 : Introduction to digital designs, Xilinx design tools, 7-segment display.  Hazards,   gray-code encoder/decoder
Week 2 : Binary Arithmetics: Adder & subtractor, Carry-lookahead and Carry-select adder
Week 3 : Introduction to D-Flip Flop, Clock, and finite state machine, finite state machine circuits: counter, traffic light controllers
Week 4 : Mini-CPU concepts / machine code, CPU control unit, ALU.

Week 5:  More advanced topics on digital designs + final exam
Final : Last day of class

Grading Policy

10% : Lab 1
15% : Lab 2
25% : Lab 3
30% : Lab 4
20% : Final Exam

Download

Webpack Download: Sorry, the files are too large. Please go to XILINX website to download the required tools. You'll need to download the free ModelSim. You will be asked to install the license for ModelSim in order to use it.

Other useful downloads:

·        Xilinx Webpack Tutorial - VHDL + ModelSim Simulation

·        A tutorial on using BUS in Xilinx ISE

·        A tutorial on creating simple finite state machine using VHDL

 

Announcements

·          8/2/06: The deadline for late turn in for lab 4 would be on Friday, 8/4/06, during the professor office hours. A 10 points penalty would be applied for the late turn in on Friday.