7.23

[10] <§7.2, B.5>

You have been given 18 32K × 16-bit SRAMs to build an

instruction cache for a processor with a 32-bit address. What is the largest size (i.e.,

the largest size of the data storage area in bytes) direct-mapped instruction cache that

you can build with one-word (64-bit) blocks? Show the breakdown of the address

into its cache access components (for an example, see Figure 7.8) and describe how

the various SRAM chips will be used. (Hint: You may not need all of them.)