Lab Assignment #4

Lab Assignment #4, Due July 29, 2002

Due 1:00PM, to be emailed to sgossin@cs.ucsd.edu

Introduction: This lab consists of two parts: (i) Implementation of two types of adders: ripple-carry adder, and carry look-ahead adder on LogicWorks and (ii) Implementation of hazard-free circuits. The second part consists of two subsections: converting a design with hazards to a hazard-free design and verification of the final design on LogicWorks via simulation.

General Information

In this experiment the delays associated with the logic gates to be used during the simulation play an important role. In the previous experiments you were using the default delay values supplied by LogicWorks. However, in this experiment we want to modify these delays to include the timings of the discrete components. Before starting this experiment please read the "Schematic Simulator Menu Commands: Delay Box" section from LogicWorks^TM4 Interactive Circuit Design Software For Windows. For each component set the delays according to the following table.

Name	Gate Delay(ns)	Name	Gate Delay(ns)
Inverter	10
AND	24	n-input AND	16 + n * 4
OR	24	n-input OR	16 + n * 4
NAND	14	n-input NAND	6 + n * 4
NOR	14	n-input NOR	6 + n * 4
XOR	42
XNOR	32

Please read the section "Device Editor" from LogicWorks^TM4 Interactive Circuit Design Software For Windows.

Part 1: Adder Implementations

The objective of this part of the exercise is to familiarize yourself with various implementations of adders. In this part of the exercise, you will implement a ripple-carry adder and a carry look-ahead adder. In both implementations you will create a standard (XOR/AND/OR) implementation and the associated NAND/NAND implementation. In all subcircuits, set the delays of the gates according to the table given in the previous General Information section.

Implement a Full-Adder using the standard implementation (using XOR/AND/OR gates) and NAND/NAND implementation. Create a subcircuit for each of these implementations. Name the implementation according to the following naming convention:

Full-Adder (standard): FA_S
Full-Adder (NAND-NAND): FA_N

Using these full adders, implement a 4-bit ripple-carry adder (one with FA_S and one with FA_N). Measure the delay of these adders for various input combinations. The delay of an adder is the time difference between the time you change the input and the time when the output does not change any more. Please include the addition of (1111 to 0001) in your delay measurements. Try to get the worst case delay (or critical path delay). In your report, describe the worst case delay (tell the inputs that cause it, and how long that delay is).

Information about ripple-carry adders can be found in your text, Gajski, Principles of Digital Design, section-5.1.

Implement a carry-look-ahead adder. Follow these steps in your implementation.

Create a subcircuit with 2 4-bit inputs to generate "generate" and "propagate" terms for carry-look-ahead adder.
Implement a carry-look-ahead generator circuit. The inputs to this circuit should be g₀...g₃, p₀...p₃ and c₀. The output of this circuit should be c₁...c₄ & g_(0,3), p_(0,3).
Combining the building blocks, create a 4-bit carry-look-ahead adder. The inputs to this circuit should be x₀...x₃, y₀...y₃ and c₀, and the outputs should be s₀...s₃ and g_(0,3), p_(0,3).

For the above implementation use both standard and NAND-NAND implementation. In effect, you will have two sets of all of the aforementioned circuits. Use _S and _N for naming convention. Measure the delay of your carry-look-ahead adder circuit using the method that you used for the ripple-carry adder.

Information about carry-look-ahead adders can be found in your text, Gajski, Principles of Digital Design, section-5.2.

Now you are going to implement 3-different 16-bit adders:

16-bit ripple-carry adder using 4-bit ripple carry adders
16-bit carry-look-ahead adder (single-level) using 4-bit look-ahead-carry adders
16-bit carry-look-ahead adder (two-level) using 4-bit look-ahead-carry adders

Please measure the critical path delays. In which implementation do you get the best delay time? In your report list the worst case delay for each 16-bit adder and the input that causes this delay.

Part 2: Logic Functions

The objective of this part of the exercise is to learn about the implementation of hazard-free circuits.

In this part you are given the following functions:

F₁(w,x,y,z) = w'z+wxy'+wy'z'
F₂(w,x,y,z) = w'x+wy+xy+w'y'z
F₃(w,x,y,z) = (x+z)(w+x')(x'+y'+z')
F₄(w,x,y,z) = (w'+y)(w+x'+z')(x'+y+z')(w'+x'+z)

Find the hazard free implementation of F₁ and F₂ in sum of products and F₃and F₄ product of sums form if the corresponding function contains static hazards. Draw the schematic of the implementation with static-hazards on Logic Works and set the delay of the components as given in the General Information section. Perform logic simulation to indicate all possible hazards in this circuit.

In your report, state the function(s) which contain(s) static hazards and what those hazards are. Now, draw the schematic of your own hazard-free implementation(s) with the same delay settings for the functions that you detected a static hazard. Verify that the previously available static-hazards are no longer there.

Information about static-hazards and implementation of hazard-free circuits can be found in your text, Gajski, Principles of Digital Design, section-4.7.

Requirements:
For the first part, turn in a all your designs together with the results that you are asked to turn in in the first part of this hand-out (delays, etc.). For the second part, indicate which functions have static hazards, describe these hazards and describe when they occur. Also, for each circuit containing a hazard, turn in a circuit that implements the same function in a hazard-free manner.