CSE 140L Hardware Lab Three

State Machine Ciruits & mini-ALU

Due date: 7/28/2001

Objectives

We will learn how to design and build state machine circuits.

Part 1. 15-second time bomb

Design a counter that starts at 15 and count to 0.
There are several input to this circuit:
  • [start] : start the counter
  • [stop] : stop the counter
  • [reset] : reset back to 15 seconds
The output should include:
  • [counter index] (in binary is OK)
  • [blow_up] indicator when the sequence reaches 0000.
You should use a D-FF that allows your to pre-set value (try FDSRE or similar ones). Note, figure out which D-FF you want to use & understand how it works before you connect all the wires together. Once you figure out how FDSRE works, you may need to add a few logics so that the time bomb does not blow up when you set start=1 initially.

Simulate with start=0 first, then switch start=1. The counter should be at 1111 & the blow_up indicator should be 0 until the counter becomes 0000. Also, simulate the case that when start=1 but you realize at 5 second before blowing up, you need to stop it & reset it back to 15 seconds again.

i. Design this counter (including MOORE state digram, state table, and K-maps, etc)
Note, remember to simplify your design as much as possible.
ii. Build and simulate the circuit using xilinx.

Part 2. Freeway Traffic Control

Around 4pm in the afternoon when much of the traffic starts to enter the freeway, a set of GREEN/RED signal are used to prevent highway jams. Here is how the traffic signal works.
  • There will be 2 lanes to enter the freeway: 1 carpool lane and 1 regular lane. Each lane will have a GREE/RED signal.
  • When both lanes have cars waiting, each lane will take turns to go (GREEN will rotate between 2 lanes).
  • When both lanes have no cars, both signal will be RED
  • When 1 lane has cars, only that lane will be GREEN. The other lane will always be RED.
i. Design this circuit (Include a MOORE state digram and briefly describe the state diagram and how it satisfies the requirement definition. Also include the state table, and K-maps, algebraic equation, and final schematic).
ii. Build the circuit and simulate is using xilinx
iii. What happens when your car breaks down on the carpool lane at the signal and it's your turn to go on GREEN light?

Part 3. Door combination

Design a circuit (using MEALY state machine) to simulate a door lock combination with the following specifications:
  • There will be 3 input buttons [0] and [1] and a [RESET] button to reset the circuit
  • There will be two output indicators (open_ind and error_ind)
  • When use enter the sequence of four : 0110, the door lock should open (open_ind = 1)
  • If two buttons are pushed at the same time, then error_ind = 1.
  • If user enter any sequences of four other than 0110, then error = 1 and circuit resets.
i. Design this circuit (Include a MEALY state digram and briefly describe the state diagram and how it satisfies the requirement definition. Also include the state table, and K-maps, algebraic equation, and final schematic).
ii. Build the circuit and simulate it using xilinx

Report
You know the drill by now!